物理不可克隆函數-多位并行異或運算一體化設計技術

李剛; 周俊杰; 汪鵬君; 張茂林; 郭宇鋒

doi:10.11999/JEIT240300

物理不可克隆函數-多位并行異或運算一體化設計技術

doi: 10.11999/JEIT240300

李剛^{1, 2},
周俊杰²,
汪鵬君²,
張茂林¹,
郭宇鋒^1, ,

1.
南京郵電大學集成電路科學與工程學院南京 210003
2.
溫州大學電氣與電子工程學院溫州 325035

基金項目: 國家自然科學基金(62374117, 62234008)，浙江省自然科學基金(LY22F040004)，中國博士后科學基金(2023M731776)，溫州市基礎性科研項目(G20240015)

詳細信息

作者簡介:
李剛：男，副教授，研究方向為集成電路設計、硬件安全

周俊杰：男，碩士生，研究方向為物理不可克隆函數設計

汪鵬君：男，教授，研究方向為集成電路設計、信息安全等技術及其相關理論

張茂林：男，講師，研究方向為超寬禁帶半導體材料、器件和功率集成

郭宇鋒：男，教授，研究方向為新型功率器件、功率和射頻集成電路與集成系統

通訊作者:
郭宇鋒　yfguo@njupt.edu.cn

中圖分類號: TN4;TP43
計量
- 文章訪問數: 225
- HTML全文瀏覽量: 75
- PDF下載量: 32
- 被引次數: 0
出版歷程
- 收稿日期: 2024-04-19
- 修回日期: 2024-08-22
- 網絡出版日期: 2024-08-30
- 刊出日期: 2024-11-01

Integrated Design Techniques of Physical Unclonable Function and Multi-bit Parallel Exclusive OR Operations

1.
College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China
2.
College of Electrical and Electronic Engineering, Wenzhou University, Wenzhou 325035, China

Funds: The National Natural Science Foundation of China (62234008, 62374117), Zhejiang Provincial Natural Science Foundation of China (LY22F040004), China Postdoctoral Science Foundation (2023M731776), Wenzhou Basic Scientific Research Projects (G20240015)

摘要

摘要: 物理不可克隆函數(PUF)和異或(XOR)運算在信息安全領域均發(fā)揮著重要作用。為突破PUF與邏輯運算之間的功能壁壘，通過對PUF工作機理和差分串聯電壓開關邏輯(DCVSL)的研究，該文提出一種基于DCVSL異或門級聯單元隨機工藝偏差的PUF和多位并行異或運算電路一體化設計方案。通過在DCVSL異或門差分輸出端增加預充電管并在對地端設置管控門，可實現PUF特征信息提取、異或/同或(XOR/XNOR)運算和功率控制3種工作模式自由切換。此外，針對PUF響應穩(wěn)定性問題，提出極端工作點和黃金工作點共同參與標記的不穩(wěn)定位混合篩選技術。基于TSMC 65 nm工藝，對輸入位寬為10位的電路進行全定制版圖設計，面積為38.76 μm²。實驗結果表明，PUF模式下，可產生1 024位輸出響應，混合篩選后可獲得超過512位穩(wěn)定的密鑰，且具有良好的隨機性和唯一性；運算模式下，可同時實現10位并行異或和同或運算，功耗和延時分別為2.67 μW和593.52 ps。功控模式下，待機功耗僅70.5 nW。所提方法為突破PUF“功能墻”提供了一種新的設計思路。
- 物理不可克隆函數 /
- 邏輯運算 /
- 一體化設計 /
- 穩(wěn)定性篩選 /
- 硬件安全
Abstract: Physical Unclonable Functions (PUFs), as well as Exclusive OR (XOR) operations, play an important role in the field of information security. In order to break through the functional barrier between PUF and logic operation, an integrated design scheme of PUF and multi-bit parallel XOR operation circuit based on the random process deviation of Differential Cascode Voltage Switch Logic (DCVSL) XOR gate cascade unit is proposed by studying the working mechanism of PUF and DCVSL. By adding a pre-charge tube at the differential output of the DCVSL XOR gate and setting a control gate at the ground end, three operating modes of the PUF feature information extraction, XOR/ Negated Exclusive OR (XNOR) operation and power control can be switched freely. Meanwhile, for the PUF response stability problem, the unstable bit hybrid screening technique with extreme and golden operating point participation labeling was proposed. Based on TSMC process of 65 nm, a fully customized layout design for a 10-bit input bit-wide circuit with an area of 38.76 μm² was carried out. The experimental results show that the 1024-bit output response can be generated in PUF mode, and a stable key of more than 512 bit can be obtained after hybrid screening, which has good randomness and uniqueness; In the operation mode, 10-bit parallel XOR and XNOR operations can be achieved simultaneously, with power consumption and delay of 2.67 μW and 593.52 ps, respectively. In power control mode, the standby power consumption is only 70.5 nW. The proposed method provides a novel way to break the function-wall of PUF.
- Physical Unclonable Functions (PUF) /
- Logical operations /
- Integrated design /
- Stability screening /
- Hardware security

HTML全文

圖 1 傳統APUF電路結構

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圖 2 基于CMOS和DCVSL的3輸入異或門

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圖 3 PUF與邏輯運算融合設計電路結構

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圖 4 多模式工作狀態(tài)

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圖 5 偏差預選

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圖 6 復合篩選示意圖與流程圖

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圖 7 PUF全定制版圖

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圖 8 邏輯運算仿真波形

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圖 9 PUF響應的隨機性

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圖 10 PUF響應的唯一性和穩(wěn)定性

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圖 11 PUF原始誤碼率和篩選后的誤碼率

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圖 12 不同篩選方式的篩選效率

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1 標記實際不穩(wěn)定位

standard_response = PUF_at (SV, ST), unstable_bits = 0
for each voltage∈ [LV, ···, SV, ···, HV] do
for each temperature ∈ [LT, ···, ST, ···, HT] do
if measured_response[i] != standard_response[i]
unstable_bits[i] = 1
end if
end for
end for

下載: 導出CSV

2 篩選不穩(wěn)定位

Filter_bits=1;
for each (voltage, temperature)∈ [(SV,ST), (LV,LT), 　(LV,HT), (HV,LT), (HV,HT)] do
for i from 1 to 2ⁿ do
if left_response[i] != right_response [i]
filter[i] = 1;
end if
end for
end for
for i from 1 to 2ⁿ do
if filter[i] ==0 and unstable_bits==1
Filter_bits++
break
end if
end for

下載: 導出CSV

表 1 與相關文獻性能對比

	VLSI’20^[16]	TCASI’22^[17]	JSSC’22^[13]	ISCAS’23^[18]	本文
工藝尺寸(nm)	65	65	28	65	65
比特特征尺寸(F²)	215	–	1125	–	8.95
電壓范圍(V)	1.0～1.4	0.5～1.0	0.75～1.05	0.7～1.5	1.0～1.4
溫度范圍(°C)	–40～125	–10～80	–25～100	0～120	–40～85
原始誤碼率(%)	2.12*	3.00	3.78	5.025*	3.82
隨機性(%)	49.30	50.11	–	50.59	49.87
唯一性	0.500 0	0.494 7	0.5030	0.499 8	0.502 8
邏輯運算	無	無	無	無	有
功率控制	無	無	無	無	有
不穩(wěn)定位篩選	無	無	無	無	有
*最大誤碼率

下載: 導出CSV

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