FPGA雙端口存儲器映射優(yōu)化算法

徐宇; 林郁; 楊海鋼

doi:10.11999/JEIT190077

FPGA雙端口存儲器映射優(yōu)化算法

doi: 10.11999/JEIT190077

徐宇^{1, 2},
林郁³,
楊海鋼^{1, 2, ,}

1.
中國科學(xué)院電子學(xué)研究所北京 100190
2.
中國科學(xué)院大學(xué) 北京 100190
3.
賽靈思電子科技北京分公司北京 100101

基金項目: 國家自然科學(xué)基金(61474120, 61404140, 61704173)

詳細信息

作者簡介:
徐宇：男，1990年生，博士生，研究方向為FPGA軟件設(shè)計自動化

林郁：男，1982年生，高級工程師，研究方向為FPGA軟件設(shè)計自動化

楊海鋼：男，1960年生，研究員/教授，博士生導(dǎo)師，研究方向微電子學(xué)與集成電路技術(shù)

通訊作者:
楊海鋼　yanghg@mail.ie.ac.cn

中圖分類號: TN43
計量
- 文章訪問數(shù): 1949
- HTML全文瀏覽量: 710
- PDF下載量: 115
- 被引次數(shù): 0
出版歷程
- 收稿日期: 2019-01-28
- 修回日期: 2020-01-20
- 網(wǎng)絡(luò)出版日期: 2020-07-20
- 刊出日期: 2020-10-13

Optimization Algorithm of Dual-port Memory Mapping on FPGA

Yu XU^{1, 2},
Yu LIN³,
Haigang YANG^{1, 2
, ,}

1.
Institute of Electrics, Chinese Academy of Sciences, Beijing 100190, China
2.
University of Chinese Academy of Sciences, Beijing 100049, China
3.
Xilinx Incorporated, Beijing 100101, China

Funds: The National Natural Science Foundation of China (61474120, 61404140, 61704173)

摘要

摘要: FPGA存儲器映射算法負責(zé)將用戶的邏輯存儲需求映射到芯片中的分布式存儲資源上實現(xiàn)。前人對雙端口存儲器的映射算法研究相對較少，成熟的商業(yè)EDA工具的映射結(jié)果仍有不少改進空間。該文分別針對面積、延時、功耗這3個常用指標，提出一種雙端口存儲器映射的優(yōu)化算法，并給出了具體配置方案。實驗表明，在面向簡單存儲需求時，與商用工具Vivado的映射結(jié)果一致；在面向復(fù)雜存儲需求時，面積優(yōu)化和功耗優(yōu)化的映射結(jié)果對比商用工具改善了至少50%。
- FPGA /
- 雙端口存儲器映射 /
- 延時優(yōu)化 /
- 面積優(yōu)化 /
- 功耗優(yōu)化
Abstract: FPGA memory mapping algorithm utilizes distributed storage resources on chip and cooperates with some auxiliary circuits to realize the different needs of users in designing logical storage functions. Previous studies on dual-port memory mapping algorithm are relatively few. There is still much space for improvement in the mapping results by mature commercial EDA tools. An optimization algorithm of dual-port memory mapping is proposed for area, delay and power consumption, and a specific configuration scheme is given. Experiments show that when facing simple storage requirements, the mapping results are consistent with those of commercial tools; when facing complex storage requirements, the mapping results of area optimization and power optimization are improved by at least 50% compared with commercial tools Vivado.
- FPGA /
- Dual-port memory mapping /
- Delay optimization /
- Area optimization /
- Power optimization

HTML全文

圖 1 AlgoPower映射算法圖示(視圖${V_k}$)

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圖 2 AlgoDelay映射算法圖示(視圖${V_k}$)

下載: 全尺寸圖片幻燈片

圖 3 ${V_{{\rm{maxR}} }}$縱向存儲器塊設(shè)計

下載: 全尺寸圖片幻燈片

圖 4 AlgoArea映射策略配置方案

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表 1 Virtex-4存儲器塊配置方式

i	索引
i	1	2	3	4	5	6	7
地址深度 d[i]	256	512	1k	2k	4k	8k	16k
地址位寬 b[i]	8	9	10	11	12	13	14
數(shù)據(jù)位寬 w[i]	72	36	18	9	4	2	1

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表 2 AlgoPower映射策略方案

序號	視圖	配置	地址端口連接	數(shù)據(jù)端口連接	譯碼/選通
#1	V1	1k×18	a9 a8 ··· a1 a0	d33 d32 ··· d17 d16	–
	V2	1k×18	a10 a9 ··· a2 a1	d25 d24 ··· d9 d8	(a0) = 0
	V3 V4	1k×18	a11 a10 ··· a3 a2	d21 d20 ··· d5 d4	(a1 a0) = 00
#2	V1	1k×18	a9 a8 ··· a1 a0	d51 d50 ··· d35 d34	–
	V2	1k×18	a10 a9 ··· a2 a1	d43 d42 ··· d27 d26	(a0) = 0
	V3 V4	1k×18	a11 a10 ··· a3 a2	d21 d20 ··· d5 d4	(a1 a0) = 01
#3	V1	1k×18	a9 a8 ··· a1 a0	d69 d68 ··· d53 d52	–
	V2	1k×18	a10 a9 ··· a2 a1	d25 d24 ··· d9 d8	(a0) = 1
	V3 V4	1k×18	a11 a10 ··· a3 a2	d21 d20 ··· d5 d4	(a1 a0) = 10
#4	V1	1k×18	a9 a8 ··· a1 a0	d87 d86 ··· d71 d70	–
	V2	1k×18	a10 a9 ··· a2 a1	d43 d42 ··· d27 d26	(a0) = 1
	V3 V4	1k×18	a11 a10 ··· a3 a2	d21 d20 ··· d5 d4	(a1 a0) = 11
#5	V1	1k×18	a9 a8 ··· a1 a0	d15 d14 ··· d1 d0	–
	V2	2k×9	a10 a9 ··· a1 a0	d7 d6 ··· d1 d0	–
	V3 V4	4k×4	a11 a10 ··· a1 a0	d3 d2 d1 d0	–

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表 3 AlgoDelay映射策略方案

序號	視圖	配置	地址端口連接	數(shù)據(jù)端口連接	譯碼/選通
#1	V1	8k×2	a12 a11 ··· a1 a0	d1 d0	(a′15 a′14) = 00
	V2	4k×4	a11 a10 ··· a1 a0	d3 d2 d1 d0	(a′14 a′13) = 00
	V3 V4	2k×8	a10 a9 ··· a1 a0	d7 d6 d5 d4 d3 d2 d1 d0	(a′13 a′12) = 00
#2	V1	8k×2	a12 a11 ··· a1 a0	d1 d0	(a′15 a′14) = 11
	V2	4k×4	a11 a10 ··· a1 a0	d3 d2 d1 d0	(a′14 a′13) = 11
	V3 V4	2k×8	a10 a9 ··· a1 a0	d7 d6 d5 d4 d3 d2 d1 d0	(a′13 a′12) = 11
#3	V1	16k×1	a12 a11 ··· a1 a0	d1	(a′15 a′14) = 01
	V2	8k×2	a11 a10 ··· a1 a0	d3 d1	(a′14 a′13) = 01
	V3 V4	4k×4	a10 a9 ··· a1 a0	d7 d5 d3 d1	(a′13 a′12) = 01
#4	V1	16k×1	a12 a11 ··· a1 a0	d0	(a′15 a′14) = 01
	V2	8k×2	a11 a10 ··· a1 a0	d2 d0	(a′14 a′13) = 01
	V3 V4	4k×4	a10 a9 ··· a1 a0	d6 d4 d2 d0	(a′13 a′12) = 01
#5	V1	4k×4	a13 a12 ··· a1 a0	d3 d2 d1 d0	(a′15 a′14) = 10
	V2	2k×8	a12 a11 ··· a1 a0	d7 d6 d5 d4 d3 d2 d1 d0	(a′14 a′13) = 10
	V3 V4	1k×16	a11 a10 ··· a1 a0	d15 d14 ··· d1 d0	(a′13 a′12) = 10

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表 4 功耗優(yōu)化實驗結(jié)果

序號	地址1	讀1	寫1	地址2	讀2	寫2	Vivado平均觸發(fā)數(shù)	AlgoPower平均觸發(fā)數(shù)	優(yōu)化比例(%)
1	10	32	32	10	32	32	1	1.00	0
2	10	32	64	10	32	256	8	1.14	85.7
3	11	16	32	10	32	256	8	1.09	86.4
4	11	16	32	10	32	128	4	1.06	73.5
5	11	16	256	10	32	128	8	1.33	83.4
6	11	32	32	10	64	64	2	1.00	50.0
7	11	32	64	10	64	128	4	1.11	72.2
8	11	16	32	11	16	128	4	1.05	73.8

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表 5 延時優(yōu)化實驗結(jié)果

序號	V1(rd)	V2(rd)	V3(wr)	V4(wr)	AlgoDelay選通級數(shù)
1	36k×4	72k×2	18k×8	9k×16	V1: 2 V2: 3
2	81k×16	324k×4	162k×8	162k×8	V1: 3 V2: 5
3	18k×4	9k×8	36k×2	18k×4	V1: 2 V2: 1
4	4k×25	2k×50	1k×100	4k×25	V1: 1 V2: 1
5	16k×4	32k×2	8k×8	4k×16	V1: 1 V2: 2

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表 6 面積優(yōu)化實驗結(jié)果

序號	地址1	讀1	寫1	地址2	讀2	寫2	Vivado使用資源	AlgoArea使用資源	優(yōu)化比例(%)
1	10	32	32	10	32	32	2	2	0
2	10	32	64	10	32	256	8	4	50
3	11	16	32	10	32	256	8	4	50
4	11	16	32	10	32	128	4	2	50
5	11	16	256	10	32	128	4	4	0
6	11	32	32	10	64	64	4	4	0
7	11	32	64	10	64	128	4	4	0
8	11	16	32	11	16	128	4	2	50

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