利用參數(shù)稀疏性的卷積神經(jīng)網(wǎng)絡(luò)計(jì)算優(yōu)化及其FPGA加速器設(shè)計(jì)
doi: 10.11999/JEIT170819
基金項(xiàng)目:
國家科技重大專項(xiàng)(2016ZX01012101)，國家自然科學(xué)基金(61572520, 61521003)
Calculation Optimization for Convolutional Neural Networks and FPGA-based Accelerator Design Using the Parameters Sparsity
Funds:
The National Science and Technology Major Project of the Ministry of Science and Technology of China (2016ZX01012101), The National Natural Science Foundation of China (61572520, 61521003)
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摘要: 針對(duì)卷積神經(jīng)網(wǎng)絡(luò)(CNN)在嵌入式端的應(yīng)用受實(shí)時(shí)性限制的問題，以及CNN卷積計(jì)算中存在較大程度的稀疏性的特性，該文提出一種基于FPGA的CNN加速器實(shí)現(xiàn)方法來提高計(jì)算速度。首先，挖掘出CNN卷積計(jì)算的稀疏性特點(diǎn)；其次，為了用好參數(shù)稀疏性，把CNN卷積計(jì)算轉(zhuǎn)換為矩陣相乘；最后，提出基于FPGA的并行矩陣乘法器的實(shí)現(xiàn)方案。在Virtex-7 VC707 FPGA上的仿真結(jié)果表明，相比于傳統(tǒng)的CNN加速器，該設(shè)計(jì)縮短了19%的計(jì)算時(shí)間。通過稀疏性來簡(jiǎn)化CNN計(jì)算過程的方式，不僅能在FPGA實(shí)現(xiàn)，也能遷移到其他嵌入式端。
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關(guān)鍵詞:
- 卷積神經(jīng)網(wǎng)絡(luò) /
- 稀疏性 /
- 計(jì)算優(yōu)化 /
- 矩陣乘法器 /
- FPGA
Abstract: Concerning the problem of real-time restriction on the application of Convolution Neural Network (CNN) in embedded field, and the large degree of sparsity in CNN convolution calculations, this paper proposes an implement method of CNN accelerator based on FPGA to improve computation speed. Firstly, the sparseness characteristics of CNN convolution calculation are seeked out. Secondly, in order to use the parameters sparseness, CNN convolution calculations are converted to matrix multiplication. Finally, the implementation method of parallel matrix multiplier based on FPGA is proposed. Simulation results on the Virtex-7 VC707 FPGA show that the design shortens the calculation time by 19% compared to the traditional CNN accelerator. The method of simplifying the CNN calculation process by sparseness not only can be implemented on FPGA, but also can migrate to other embedded ends.-
Key words:
- Convolution Neural Network (CNN) /
- Sparseness /
- Computational optimization /
- Matrix multiplier /
- FPGA
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