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橢圓曲線密碼處理器的高效并行處理架構(gòu)研究與設計

戴紫彬,  易肅汶,  李偉,  南龍梅

戴紫彬, 易肅汶, 李偉, 南龍梅. 橢圓曲線密碼處理器的高效并行處理架構(gòu)研究與設計[J]. 電子與信息學報, 2017, 39(10): 2487-2494. doi: 10.11999/JEIT161380
引用本文: 戴紫彬, 易肅汶, 李偉, 南龍梅. 橢圓曲線密碼處理器的高效并行處理架構(gòu)研究與設計[J]. 電子與信息學報, 2017, 39(10): 2487-2494. doi: 10.11999/JEIT161380
DAI Zibin, YI Suwen, LI Wei, NAN Longmei. Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2487-2494. doi: 10.11999/JEIT161380
Citation: DAI Zibin, YI Suwen, LI Wei, NAN Longmei. Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor[J]. Journal of Electronics & Information Technology, 2017, 39(10): 2487-2494. doi: 10.11999/JEIT161380

橢圓曲線密碼處理器的高效并行處理架構(gòu)研究與設計

doi: 10.11999/JEIT161380
  • 1.

    (解放軍信息工程大學 鄭州 450000) ②(復旦大學專用集成電路與系統(tǒng)國家重點實驗室 上海 201203)

基金項目: 

國家自然科學基金(61404175)

Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor

  • 1.

    (PLA Information Engineering University, Zhengzhou 450000, China)

Funds: 

The National Natural Science Foundation of China (61404175)

  • 摘要: 為了解決當前橢圓曲線密碼處理器普遍存在靈活性低、資源占用大的問題，該文采用統(tǒng)計建模的方式，以面積-時間(AT)綜合性能指標為指導，提出了一種面向橢圓曲線密碼并行處理架構(gòu)的量化評估方式，并確定3路異構(gòu)并行處理架構(gòu)可使處理器綜合性能達到最優(yōu)。其次，該文提出一個分離分級式存儲結(jié)構(gòu)和一個運算資源高度復用的模運算單元，可增強存儲器的訪問效率和運算資源的利用率。在90 nm CMOS工藝下綜合，該文處理器的面積為1.62mm2，完成一次GF(2571)和GF(p521)上的點乘運算分別需要2.26 ms/612.4J和2.63 ms/665.4J。與同類設計相比，該文處理器不僅具有較高的靈活性、可伸縮性，而且其芯片面積和運算速度達到了很好的折中。
    Abstract: To overcome the common problem of low flexibility and much resource in Elliptic Curve Cryptographic (ECC) processor, a quantitative evaluation on Area-Time product (AT) for parallel processing architecture of ECC processor is proposed by statistics and modeling, and a conclusion that 3-way processing architecture is optimal can be drawn. Besides, a separated and hierarchical storage structure is exploited to strengthen the efficiency of data interaction. At the same time, a modular arithmetic unit is designed with a high level of resource reuse. Using 90 nm CMOS technology, the proposed processor occupied1.62mm2 can perform the scalar multiplication in2.26 ms/612.4J overGF(2571) and 2.63 ms/665.4 J overGF(p521), respectively. Compared to other works, this processor is advantageous not only in flexibility and scalability but also in making a good compromise between the hardware and the speed.
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出版歷程
  • 收稿日期:  2016-12-21
  • 修回日期:  2017-03-06
  • 刊出日期:  2017-10-19

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