反演光刻技術(shù)的研究進(jìn)展

艾飛; 蘇曉菁; 韋亞一

doi:10.11999/JEIT240308

反演光刻技術(shù)的研究進(jìn)展

doi: 10.11999/JEIT240308

艾飛¹,
蘇曉菁^{1, 2},
韋亞一^{1, 2, ,}

1.
中國(guó)科學(xué)院大學(xué)集成電路學(xué)院北京 100049
2.
中國(guó)科學(xué)院微電子研究所北京 100029

基金項(xiàng)目: 國(guó)家自然科學(xué)基金 (62204257)，中央高校基本科研業(yè)務(wù)費(fèi)專項(xiàng)資金(E3E43802)，中國(guó)科學(xué)院青促會(huì)項(xiàng)目(2021115)

詳細(xì)信息

作者簡(jiǎn)介:
艾飛：男，博士，特別研究助理，研究方向?yàn)橛?jì)算光刻

蘇曉菁：女，副研究員，研究方向?yàn)橛?jì)算光刻，設(shè)計(jì)與工藝協(xié)同優(yōu)化

韋亞一：男，特聘教授，研究方向?yàn)榧呻娐芳夹g(shù)

通訊作者:
韋亞一　weiyayi@ime.ac.cn

中圖分類號(hào): TN405; TP301
計(jì)量
- 文章訪問(wèn)數(shù): 389
- HTML全文瀏覽量: 177
- PDF下載量: 48
- 被引次數(shù): 0
出版歷程
- 收稿日期: 2024-04-22
- 修回日期: 2024-12-06
- 網(wǎng)絡(luò)出版日期: 2024-12-12
- 刊出日期: 2025-01-31

Research Progress of Inverse Lithography Technology

AI Fei¹,
SU Xiaojing^{1, 2},
WEI Yayi^{1, 2
, ,}

1.
School of integrated circuits, University of Chinese Academy of Sciences, Beijing 100049, China
2.
Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China

Funds: The National Natural Science Foundation of China (62204257), The Fundamental Research Funds for the Central Universities (E3E43802), The Youth Innovation Promotion Association Chinese Academy of Sciences (2021115)

摘要

摘要: 反演光刻技術(shù)(ILT)相比傳統(tǒng)的光學(xué)臨近效應(yīng)修正(OPC)，生成的掩模具有成像效果更好，工藝窗口更大等優(yōu)點(diǎn)，在當(dāng)前芯片制造的工藝尺寸不斷減小的背景下，逐漸成為主流的光刻掩模修正技術(shù)。該文首先介紹了反演光刻算法的基本原理和幾種主流實(shí)現(xiàn)方法；其次，調(diào)研了當(dāng)前反演光刻技術(shù)應(yīng)用在光刻掩模優(yōu)化問(wèn)題上的研究進(jìn)展，分析了反演光刻技術(shù)的優(yōu)勢(shì)和存在的問(wèn)題。以希望為計(jì)算光刻及相關(guān)研究領(lǐng)域的研究人員提供參考，為我國(guó)先進(jìn)集成電路產(chǎn)業(yè)的發(fā)展提供技術(shù)支持。
- 先進(jìn)集成電路技術(shù) /
- 反演光刻技術(shù) /
- 光學(xué)臨近效應(yīng)修正 /
- 掩模優(yōu)化 /
- 研究進(jìn)展
Abstract: Objective Inverse Lithography Technology (ILT) provides improved imaging effects and a larger process window compared to traditional Optical Proximity Correction (OPC). As chip manufacturing continually reduces process dimensions, ILT has become the leading lithography mask correction technology. This paper first introduces the basic principles and several common implementation methods of the reverse lithography algorithm. It then reviews current research on using reverse lithography technology to optimize lithography masks, as well as analyzes the advantages and existing challenges of this technology. Methods The general process of generating mask patterns in ILT is exemplified using the level set method. First, the target graphics, light sources, and other inputs are identified. Then, the initial mask pattern is created and a pixelated model is constructed. A photolithography model is then established to calculate the aerial image. The general photoresist threshold model is represented by a sigmoid function, which helps derive the imaging pattern on the photoresist. The key element of the ILT algorithm is the cost function, which measures the difference between the wafer image and the target image. The optimization direction is determined based on the chosen cost function. For instance, the continuous cost function can calculate gradients, enabling the use of gradient descent to find the optimal solution. Finally, when the cost function reaches its minimum, the output mask is generated. Results and Discussions This paper systematically introduces several primary methods for implementing ILT. The level set method’s main concept is to convert a two-dimensional closed curve into a three-dimensional surface. Here, the closed curve is viewed as the set of intersection lines between the surface and the zero plane. During the ILT optimization process, the three-dimensional surface shape remains continuous. This continuity allows the ILT problem to be transformed into a multivariate optimization problem, solvable using gradient algorithms, machine learning, and other methods. Examples of the level set method’s application can be found in both mask optimization and light source optimization. The level set mathematical framework effectively addresses two-dimensional curve evolution. When designing the ILT algorithm, a lithography model determines the optimization direction and velocity for each mask point, employing the level set for mask evolution. Intel has proposed an algorithm that utilizes a pixelated model to optimize the entire chip. However, this approach incurs significant computational costs, necessitating larger mask pixel sizes. Notably, the pixelated model is consistently used throughout the process, with a defined pixelated cost function applicable to multi-color masks. The frequency domain method for calculating the ILT curve involves transforming the mask from the spatial domain into the frequency domain, followed by lithography model calculations. This approach generates a mask with continuous pixel values, which is then gradually converted into a binary mask through multiple steps. When modifying the cost function in frequency domain optimization, all symmetric and repetitive patterns are altered uniformly, preserving symmetry. The transition of complex convolution calculations into multiplication processes within the frequency domain significantly reduces computational complexity and can be accelerated using GPU technology. Due to the prevalent issue of high computational complexity in various lithography mask optimization algorithms, scholars have long pursued machine learning solutions for mask optimization. Early research often overlooked the physical model of photolithography technology, training neural networks solely based on optimized mask features. This oversight led to challenges such as narrow process windows. Recent studies have, however, integrated machine learning with other techniques, enabling the physical model of lithography technology to influence neural network training, resulting in improved optimization results. While the ILT-optimized mask lithography process window is relatively large, its high computational complexity limits widespread application. Therefore, combining machine learning with the ILT method represents a promising research direction. Conclusions Three primary techniques exist for optimizing masks using ILT: the Level Set Method, Intel Pixelated ILT Method, and Frequency Domain Calculation of Curve ILT. The Level Set Method reformulates the ILT challenge into a multivariate optimization issue, utilizing a continuous cost function. This approach allows for the application of established methods like gradient descent, which has attracted significant attention and is well-documented in the literature. In contrast, the Intel method relies entirely on pixelated models and pixelated cost functions, though relevant literature on this method is limited. Techniques in the frequency domain can leverage GPU operations to substantially enhance computational speed, and advanced algorithms also exist for converting curve masks into Manhattan masks. The integration of ILT with machine learning technologies shows considerable potential for development. Further research is necessary to effectively reduce computational complexity while ensuring optimal results. Currently, ILT technology faces challenges such as high computational demands and obstacles in full layout optimization. Collaboration among experts and scholars in integrated circuit design and related fields is essential to improve ILT computational speed and to integrate it with other technologies. We believe that as research on ILT-related technologies advances, it will play a crucial role in helping China’s chip industry overcome technological bottlenecks in the future.
- Advanced integrated circuit technology /
- Reverse lithography technology /
- Optical proximity effect correction /
- Mask optimization /
- Research progress

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圖 1 ILT優(yōu)化掩模示意圖

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圖 2 ILT算法的一般流程

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圖 3 Level set方法生成SRAF示意圖^[48]

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圖 4 Level set 方法生成掩模圖形的一般流程^[49,50]

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圖 5 使用OPC和ILT優(yōu)化45 nm FLASH的結(jié)果^[50]

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圖 6 使用OPC(未插入SRAF)和ILT(插入SRAF)優(yōu)化45 nm SRAM連接層^[50]

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圖 7 相同目標(biāo)圖形在不同光源下利用Level set ILT方法生成的掩模圖形^[50]

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圖 8 Intel像素化ILT流程示意圖^[51]

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圖 9 Intel像素化ILT雙色掩模優(yōu)化結(jié)果^[51]

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圖 10 連續(xù)的像素化掩模二值化過(guò)程^[10]

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圖 11 OPC與頻域中計(jì)算曲線 ILT方法的對(duì)比^[52]

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圖 12 基于梯度的ILT計(jì)算流程示意圖^[66]

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圖 13 模型驅(qū)動(dòng)神經(jīng)網(wǎng)絡(luò)方法示意圖^[66]

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圖 14 一種基線CGAN ILT框架圖^[70]

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圖 15 包含光刻物理模型信息的深度學(xué)習(xí)網(wǎng)絡(luò)ILT方法流程示意圖^[72]

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