SMCA：基于芯粒集成的存算一體加速器擴(kuò)展框架

李雯; 王穎; 何銀濤; 鄒凱偉; 李華偉; 李曉維

doi:10.11999/JEIT240284

SMCA：基于芯粒集成的存算一體加速器擴(kuò)展框架

doi: 10.11999/JEIT240284

李雯^{1, 2, 3},
王穎^{4, 5, ,},
何銀濤^{4, 5},
鄒凱偉⁶,
李華偉^{4, 5},
李曉維^{4, 5}

1.
山西大學(xué)計(jì)算機(jī)與信息技術(shù)學(xué)院(大數(shù)據(jù)學(xué)院) 太原 030006
2.
山西大學(xué)大數(shù)據(jù)科學(xué)與產(chǎn)業(yè)研究院太原 030006
3.
山西大學(xué)計(jì)算智能與中文信息處理教育部重點(diǎn)實(shí)驗(yàn)室太原 030006
4.
中國(guó)科學(xué)院計(jì)算技術(shù)研究所處理器芯片全國(guó)重點(diǎn)實(shí)驗(yàn)室北京 100190
5.
中國(guó)科學(xué)院大學(xué) 北京 100190
6.
清華大學(xué)電子工程系北京 100084

基金項(xiàng)目: 國(guó)家自然科學(xué)基金(62302283)，山西省基礎(chǔ)研究計(jì)劃項(xiàng)目(自由探索類)(202303021212015)

詳細(xì)信息

作者簡(jiǎn)介:
李雯：女，講師，研究方向?yàn)槿蒎e(cuò)計(jì)算和集成電路設(shè)計(jì)

王穎：男，研究員，研究方向?yàn)樾滦虴DA、處理器與存儲(chǔ)系統(tǒng)體系結(jié)構(gòu)

何銀濤：女，博士生，研究方向?yàn)榇嫠阋惑w芯片、專用處理器設(shè)計(jì)

鄒凱偉：女，博士后，研究方向?yàn)橹悄苄酒O(shè)計(jì)

李華偉：女，研究員，研究方向?yàn)閂LSI測(cè)試、容錯(cuò)計(jì)算

李曉維：男，研究員，研究方向?yàn)橛布踩?、集成電路設(shè)計(jì)自動(dòng)化

通訊作者:
王穎　wangying2009@ict.ac.cn

中圖分類號(hào): TN40; TP389.1
計(jì)量
- 文章訪問(wèn)數(shù): 407
- HTML全文瀏覽量: 155
- PDF下載量: 67
- 被引次數(shù): 0
出版歷程
- 收稿日期: 2024-04-16
- 修回日期: 2024-09-13
- 網(wǎng)絡(luò)出版日期: 2024-09-30
- 刊出日期: 2024-11-01

SMCA: A Framework for Scaling Chiplet-Based Computing-in-Memory Accelerators

LI Wen^{1, 2, 3},
WANG Ying^{4, 5
, ,},
HE Yintao^{4, 5},
ZOU Kaiwei⁶,
LI Huawei^{4, 5},
LI Xiaowei^{4, 5}

1.
School of Computer and Information Technology (School of Big Data), Shanxi University Taiyuan 030006, China
2.
Institute of Big Data Science and Industry, Shanxi University Taiyuan 030006, China
3.
Key Laboratory of Computational Intelligence and Chinese Information Processing of Ministry of Education, Shanxi University Taiyuan 030006, China
4.
State Key Laboratory of Processors, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
5.
University of Chinese Academy of Sciences, BeiJing 100190, China
6.
Department of Electronic Engineering, Tsinghua University, Beijing 100084, China

Funds: The National Natural Science Foundation of China (62302283), The Basic Research Program of Shanxi Province (Exploration Research)(202303021212015)

摘要

摘要: 基于可變電阻式隨機(jī)存取存儲(chǔ)器(ReRAM)的存算一體芯片已經(jīng)成為加速深度學(xué)習(xí)應(yīng)用的一種高效解決方案。隨著智能化應(yīng)用的不斷發(fā)展，規(guī)模越來(lái)越大的深度學(xué)習(xí)模型對(duì)處理平臺(tái)的計(jì)算和存儲(chǔ)資源提出了更高的要求。然而，由于ReRAM器件的非理想性，基于ReRAM的大規(guī)模計(jì)算芯片面臨著低良率與低可靠性的嚴(yán)峻挑戰(zhàn)。多芯粒集成的芯片架構(gòu)通過(guò)將多個(gè)小芯粒封裝到單個(gè)芯片中，提高了芯片良率、降低了芯片制造成本，已經(jīng)成為芯片設(shè)計(jì)的主要發(fā)展趨勢(shì)。然而，相比于單片式芯片數(shù)據(jù)的片上傳輸，芯粒間的昂貴通信成為多芯粒集成芯片的性能瓶頸，限制了集成芯片的算力擴(kuò)展。因此，該文提出一種基于芯粒集成的存算一體加速器擴(kuò)展框架—SMCA。該框架通過(guò)對(duì)深度學(xué)習(xí)計(jì)算任務(wù)的自適應(yīng)劃分和基于可滿足性模理論(SMT)的自動(dòng)化任務(wù)部署，在芯粒集成的深度學(xué)習(xí)加速器上生成高能效、低傳輸開銷的工作負(fù)載調(diào)度方案，實(shí)現(xiàn)系統(tǒng)性能與能效的有效提升。實(shí)驗(yàn)結(jié)果表明，與現(xiàn)有策略相比，SMCA為深度學(xué)習(xí)任務(wù)在集成芯片上自動(dòng)生成的調(diào)度優(yōu)化方案可以降低35%的芯粒間通信能耗。
- 芯粒 /
- 深度學(xué)習(xí)處理器 /
- 存算一體 /
- 任務(wù)調(diào)度
Abstract: Computing-in-Memory (CiM) architectures based on Resistive Random Access Memory (ReRAM) have been recognized as a promising solution to accelerate deep learning applications. As intelligent applications continue to evolve, deep learning models become larger and larger, which imposes higher demands on the computational and storage resources on processing platforms. However, due to the non-idealism of ReRAM, large-scale ReRAM-based computing systems face severe challenges of low yield and reliability. Chiplet-based architectures assemble multiple small chiplets into a single package, providing higher fabrication yield and lower manufacturing costs, which has become a primary trend in chip design. However, compared to on-chip wiring, the expensive inter-chiplet communication becomes a performance bottleneck for chiplet-based systems which limits the chip’s scalability. As the countermeasure, a novel scaling framework for chiplet-based CiM accelerators, SMCA (SMT-based CiM chiplet Acceleration) is proposed in this paper. This framework comprises an adaptive deep learning task partition strategy and an automated SMT-based workload deployment to generate the most energy-efficient DNN workload scheduling strategy with the minimum data transmission on chiplet-based deep learning accelerators, achieving effective improvement in system performance and efficiency. Experimental results show that compared to existing strategies, the SMCA-generated automatically schedule strategy can reduce the energy costs of inter-chiplet communication by 35%.
- Chiplet /
- Deep learning processor /
- Computing-in-Memory (CiM) /
- Task dispatching

HTML全文

圖 1 在 ReRAM 交叉陣列上執(zhí)行卷積計(jì)算的示意圖

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圖 2 SMCA 工作流程

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圖 3 同構(gòu)存算一體芯粒集成的深度學(xué)習(xí)芯片架構(gòu)

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圖 4 深度學(xué)習(xí)計(jì)算任務(wù)的平均劃分策略

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圖 5 CAP 策略與 CMP 策略的對(duì)比

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圖 6 歸一化的 NoP 能耗

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圖 7 歸一化的 NoP 時(shí)延

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圖 8 不同大小芯粒、不同規(guī)模系統(tǒng)的集成芯片上的 NoP 能耗對(duì)比

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1 自適應(yīng)層級(jí)網(wǎng)絡(luò)劃分策略

　1: 輸入：?jiǎn)蝹€(gè)芯粒的固定算力M；網(wǎng)絡(luò)$l({l_0},{l_1}, \cdots,{l_{L - 1}}) $的算力
　需求$w({w_0},{w_1}, \cdots ,{w_{L - 1}}) $。

　2: 輸出：網(wǎng)絡(luò)劃分策略bestP。

　3: ${C_{{\text{idle}}}}{{ = M}} $; /*初始化${C_{{\text{idle}}}} $*/

　4: for $i = 0,1, \cdots ,L - 1 $

　5: 　if ${C_{{\text{idle}}}} \ge {w_i} $ then

　6: 　　${\text{bestP}} \leftarrow {\text{NoPartition}}(i{\text{,}}{w_i}) $;

　7: 　else if $\left\lceil {\dfrac{{{w_i}}}{{{M}}} = = \dfrac{{{w_i} - {C_{{\text{idle}}}}}}{{{M}}}} \right\rceil $ then

　8: 　　${\text{bestP}} \leftarrow {\text{CMP}}(i{\text{,}}{w_i}) $;

　9: 　else

　10: 　 ${\text{bestP}} \leftarrow {\text{CAP}}(i{\text{,}}{w_i}) $;

　11: Update(${C_{{\text{idle}}}} $)

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表 1 SMT約束中的符號(hào)表示

符號(hào)	含義
$ {T},{E},{C} $	計(jì)算任務(wù)集合，計(jì)算圖中邊的集合以及芯片封裝的芯粒集合
$ t,c $	計(jì)算任務(wù)$ t $，芯粒$ c $
$ {e}_{i,j} $	計(jì)算圖中，任務(wù)$ i $到任務(wù)$ j $的有向邊
$ {x}^{c},\;{y}^{c} $	芯粒$ c $在芯片上的$ \left(x,y\right) $坐標(biāo)
$ {w}^{t} $	任務(wù)$ t $的計(jì)算需求
$ {o}^{t} $	任務(wù)$ t $計(jì)算產(chǎn)生的中間數(shù)據(jù)量
$ {s}^{t} $	任務(wù)$ t $的開始執(zhí)行時(shí)間
$ q7j3ldu95^{t} $	完成任務(wù)t所有前置任務(wù)所需的芯粒間最小數(shù)據(jù)傳輸開銷
$ {\tau }^{t} $	任務(wù)$ t $的執(zhí)行時(shí)間
$ \mathrm{s}{\mathrm{w}}^{c} $	芯粒$ c $所在的波前編號(hào)
$ \mathrmq7j3ldu95\mathrm{i}\mathrm{s}({c}_{i},{c}_{j}) $	芯粒$ i $到芯粒$ j $的距離

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表 2 系統(tǒng)配置

架構(gòu)層次	屬性	參數(shù)
封裝	頻率	1.8 GHz
	芯粒間互聯(lián)網(wǎng)絡(luò)帶寬	100 Gb/s
	芯粒間通信能耗	1.75 p/bit
芯粒	工藝制程	16 nm
	單個(gè)芯粒包含的計(jì)算核個(gè)數(shù)	16
	單個(gè)計(jì)算核包含的ReRAM交叉陣列個(gè)數(shù)	16
計(jì)算核	ReRAM交叉陣列大小	128$ \times $128
	ADC	1 bit
	DAC	8 bit
	一個(gè)ReRAM單元存儲(chǔ)的位數(shù)	2
	權(quán)重精度	8 bit
	數(shù)據(jù)流	權(quán)重固定型

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