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復(fù)值Hopfield神經(jīng)網(wǎng)絡(luò)的信號(hào)盲檢測一步計(jì)算電路

洪慶輝,  孫辰,  肖平旦,  韋正苗,  杜四春

洪慶輝, 孫辰, 肖平旦, 韋正苗, 杜四春. 復(fù)值Hopfield神經(jīng)網(wǎng)絡(luò)的信號(hào)盲檢測一步計(jì)算電路[J]. 電子與信息學(xué)報(bào), 2024, 46(11): 4123-4131. doi: 10.11999/JEIT240224
引用本文: 洪慶輝, 孫辰, 肖平旦, 韋正苗, 杜四春. 復(fù)值Hopfield神經(jīng)網(wǎng)絡(luò)的信號(hào)盲檢測一步計(jì)算電路[J]. 電子與信息學(xué)報(bào), 2024, 46(11): 4123-4131. doi: 10.11999/JEIT240224
HONG Qinghui, SUN Chen, XIAO Pingdan, WEI Zhengmiao, DU Sichun. One-step Calculation Circuit of Blind Signal Detection using Complex-valued Hopfield Neural Network[J]. Journal of Electronics & Information Technology, 2024, 46(11): 4123-4131. doi: 10.11999/JEIT240224
Citation: HONG Qinghui, SUN Chen, XIAO Pingdan, WEI Zhengmiao, DU Sichun. One-step Calculation Circuit of Blind Signal Detection using Complex-valued Hopfield Neural Network[J]. Journal of Electronics & Information Technology, 2024, 46(11): 4123-4131. doi: 10.11999/JEIT240224

復(fù)值Hopfield神經(jīng)網(wǎng)絡(luò)的信號(hào)盲檢測一步計(jì)算電路

doi: 10.11999/JEIT240224

  • 湖南大學(xué)信息科學(xué)與工程學(xué)院 長沙 410082

基金項(xiàng)目: 國家自然科學(xué)基金(62234008, 62371186)，湖湘青年英才項(xiàng)目(2023RC3103)，湖南省自然科學(xué)基金(2023JJ30168, 2022JJ30160, 2021JJ40111)，國家重點(diǎn)研發(fā)計(jì)劃(2022YFB3903800)
詳細(xì)信息
    作者簡介:

    洪慶輝：男，副教授，研究方向?yàn)槟M存算一體電路設(shè)計(jì)及應(yīng)用

    孫辰：男，碩士生，研究方向?yàn)閺?fù)數(shù)神經(jīng)網(wǎng)絡(luò)電路設(shè)計(jì)

    肖平旦：男，博士生，研究方向?yàn)榛趹涀杵鞯拇鎯?nèi)計(jì)算電路設(shè)計(jì)及其應(yīng)用

    韋正苗：男，博士生，研究方向?yàn)槟M電路求解矩陣方程的新方法及其應(yīng)用

    杜四春：男，副教授，研究方向?yàn)槟M/混合、射頻集成電路設(shè)計(jì)

    通訊作者:

    杜四春　jt_dsc@hnu.edu.cn

  • 中圖分類號(hào): TN402

One-step Calculation Circuit of Blind Signal Detection using Complex-valued Hopfield Neural Network

  • College of Information Science and Engineering, Hunan University, Changsha 410082, China

Funds: The National Natural Science Foundation of China (62234008, 62371186), Huxiang Young Talents Project (2023RC3103), The Natural Science Foundation of Hunan Province(2023JJ30168, 2022JJ30160, 2021JJ40111), The National Key R&D Program of China (2022YFB3903800)
  • 摘要: 信號(hào)盲檢測在大規(guī)模通信網(wǎng)絡(luò)中具有重要的意義并得到了廣泛的應(yīng)用，如何快速得到信號(hào)盲檢測結(jié)果是新一代實(shí)時(shí)通信網(wǎng)絡(luò)的迫切需求。為此，該文從模擬電路的角度設(shè)計(jì)了一種能加速信號(hào)盲檢測的復(fù)值Hopfield神經(jīng)網(wǎng)絡(luò)(CHNN)電路，該電路可一步完成大規(guī)模并行計(jì)算，提高信號(hào)盲檢測速度，同時(shí)該電路可以通過調(diào)整憶阻器的電導(dǎo)和輸入電壓來實(shí)現(xiàn)可編程功能。Pspice仿真結(jié)果表明，該電路的計(jì)算精度可達(dá)99%以上，運(yùn)行時(shí)間比Matlab軟件仿真快3個(gè)數(shù)量級(jí)，此外，該電路具有良好的魯棒性，即使在20%的噪聲干擾下，仍能保持99%以上的計(jì)算精度。
    Abstract: Blind signal detection is of great significance in large-scale communication networks and has been widely used. How to quickly obtain blind signal detection results is an urgent need for the new generation of real-time communication networks. Considering this demand, a Complex-valued Hopfield Neural Network (CHNN) circuit is designed that can accelerate blind signal detection from an analog circuit perspective, the proposed circuit can accelerate the blind signal detection by rapidly performing massively parallel calculation in one step. At the same time, the circuit can be programmable by adjusting the conductance and input voltage of the memristor. The Pspice simulation results show that the computing accuracy of the proposed circuit can exceed 99%. Compared with Matlab software simulation, the proposed circuit is three orders of magnitude faster in terms of computing time. And the accuracy can be maintained at more than 99% even under the interference of 20% noise.
    • HTML全文

  • 圖  1  信號(hào)盲檢測的處理過程

    圖  2  K=8時(shí)的復(fù)值激活函數(shù)

    圖  3  復(fù)值乘法電路

    圖  4  復(fù)值激活函數(shù)電路

    圖  5  復(fù)值激活函數(shù)電路輸出結(jié)果

    圖  6  信號(hào)盲檢測CHNN電路

    圖  7  憶阻器的兩種模式

    圖  8  CHNN電路處理流程圖

    圖  9  CHNN電路的輸出結(jié)果

    圖  10  電路精度及BER性能比較

    圖  11  電壓噪聲波形及噪聲干擾下電路的精度

    圖  12  線電阻干擾下電路的精度

    圖  13  不同隨機(jī)誤差條件下電路的平均精度

    圖  14  憶阻器編程失敗情況下電路的平均精度

    表  1  電路和軟件計(jì)算時(shí)間比較(ms)

    輸入信號(hào)數(shù)量計(jì)算時(shí)間
    PspiceMatlab
    5 階0.0019.5
    10 階0.0310.8
    20 階0.0411.2
    40 階0.0713.3
    80 階0.1615.2
    下載: 導(dǎo)出CSV

    表  2  不同硬件的計(jì)算時(shí)間

    方式其他電路[19]FPGA[22]DSP[22]
    計(jì)算時(shí)間8.2$ \times $3.8$ \times $8.2$ \times $
    下載: 導(dǎo)出CSV
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  • 收稿日期:  2024-03-29
  • 修回日期:  2024-10-10
  • 網(wǎng)絡(luò)出版日期:  2024-10-16
  • 刊出日期:  2024-11-01

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