兩種面向宇航應(yīng)用的高可靠性抗輻射加固技術(shù)靜態(tài)隨機(jī)存儲(chǔ)器單元

閆愛(ài)斌; 李坤; 黃正峰; 倪天明; 徐輝

doi:10.11999/JEIT240082

兩種面向宇航應(yīng)用的高可靠性抗輻射加固技術(shù)靜態(tài)隨機(jī)存儲(chǔ)器單元

doi: 10.11999/JEIT240082

1.
合肥工業(yè)大學(xué)微電子學(xué)院合肥 230601
2.
安徽工程大學(xué)集成電路學(xué)院蕪湖 241000
3.
安徽理工大學(xué)計(jì)算機(jī)科學(xué)與工程學(xué)院淮南 232001

基金項(xiàng)目: 國(guó)家自然科學(xué)基金(61974001)

詳細(xì)信息

作者簡(jiǎn)介:
閆愛(ài)斌：男，博士，教授，研究方向?yàn)閿?shù)字電路可靠性技術(shù)等

李坤：男，碩士生，研究方向?yàn)镾RAM單元容錯(cuò)技術(shù)

黃正峰：男，博士，教授，研究方向?yàn)閿?shù)字集成電路容錯(cuò)設(shè)計(jì)等

倪天明：男，博士，教授，研究方向?yàn)閿?shù)字集成電路可測(cè)性設(shè)計(jì)等

徐輝：男，博士，教授，研究方向?yàn)榭尚庞?jì)算與人工智能等

通訊作者:
徐輝　austxuhui@163.com

中圖分類號(hào): TN43
計(jì)量
- 文章訪問(wèn)數(shù): 288
- HTML全文瀏覽量: 95
- PDF下載量: 50
- 被引次數(shù): 0
出版歷程
- 收稿日期: 2024-02-04
- 修回日期: 2024-09-11
- 網(wǎng)絡(luò)出版日期: 2024-09-16
- 刊出日期: 2024-10-30

Two Highly Reliable Radiation Hardened By Design Static Random Access Memory Cells for Aerospace Applications

1.
School of Microelectronics, Hefei University of Technology, Hefei 230601, China
2.
School of Integrated Circuit, Anhui University of Engineering, Wuhu 241000, China
3.
School of Computer Science and Engineering, Anhui University of Science and Technology, Huainan 232001, China

Funds: The National Natural Science Foundation of China (61974001)

摘要

摘要: CMOS尺寸的大幅縮小引發(fā)電路可靠性問(wèn)題。該文介紹了兩種高可靠的基于設(shè)計(jì)的抗輻射加固(RHBD)10T和12T抗輻射加固技術(shù)(SRAM)單元，它們可以防護(hù)單節(jié)點(diǎn)翻轉(zhuǎn)(SNU)和雙節(jié)點(diǎn)翻轉(zhuǎn)(DNU)。10T單元主要由兩個(gè)交叉耦合的輸入分離反相器組成，該單元可以通過(guò)其內(nèi)部節(jié)點(diǎn)之間的反饋機(jī)制穩(wěn)定地保持存儲(chǔ)的值。由于僅使用少量晶體管，因此其在面積和功耗方面開(kāi)銷也較低?；?0T單元，提出了使用4個(gè)并行存取訪問(wèn)管的12T單元。與10T單元相比，12T單元的讀/寫訪問(wèn)時(shí)間更短，且具有相同的容錯(cuò)能力。仿真結(jié)果表明，所提單元可以從任意SNU和部分DNU中恢復(fù)。此外，與先進(jìn)的加固SRAM單元相比，所提RHBD 12T單元平均可以節(jié)省16.8%的寫訪問(wèn)時(shí)間、56.4%的讀訪問(wèn)時(shí)間和10.2%的功耗，而平均犧牲了5.32%的硅面積。
- CMOS /
- 靜態(tài)隨機(jī)存儲(chǔ)器單元 /
- 抗輻射加固 /
- 單節(jié)點(diǎn)翻轉(zhuǎn) /
- 雙節(jié)點(diǎn)翻轉(zhuǎn)
Abstract: Aggressive scaling of CMOS technologies can cause the reliability issues of circuits. Two highly reliable Radiation Hardened By Design (RHBD) 10T and 12T Static Random-Access Memory (SRAM) cells are presented in this paper, which can protect against Single Node Upsets (SNUs) and Double Node Upsets (DNUs). The 10T cell mainly consists of two cross-coupled input-split inverters and the cell can robustly keep stored values through a feedback mechanism among its internal nodes. It also has a low cost in terms of area and power consumption, since it uses only a few transistors. Based on the 10T cell, a 12T cell is proposed that uses four parallel access transistors. The 12T cell has a reduced read/write access time with the same soft error tolerance when compared to the 10T cell. Simulation results demonstrate that the proposed cells can recover from SNUs and a part of DNUs. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed RHBD 12T cell can save 16.8% write access time, 56.4% read access time, and 10.2% power dissipation at the cost of 5.32% silicon area on average.
- CMOS /
- Static Random Access Memory (SRAM) cell /
- Radiation hardening /
- Single node upset /
- Double node upset

HTML全文

圖 1 所提RHBD10T單元電路圖

下載: 全尺寸圖片幻燈片

圖 2 所提RHBD10T單元版圖

下載: 全尺寸圖片幻燈片

圖 3 所提RHBD10T單元正常操作的仿真結(jié)果

下載: 全尺寸圖片幻燈片

圖 4 所提 RHBD10T單元的SNU自恢復(fù)仿真結(jié)果

下載: 全尺寸圖片幻燈片

圖 5 所提 RHBD10T 單元的 DNU 的仿真結(jié)果

下載: 全尺寸圖片幻燈片

圖 6 所提RHBD12T單元電路圖

下載: 全尺寸圖片幻燈片

圖 7 所提 RHBD12T單元的版圖

下載: 全尺寸圖片幻燈片

圖 8 溫度與電壓變化對(duì) SRAM 設(shè)計(jì)的 RAT,WAT 和功耗影響的仿真結(jié)果

下載: 全尺寸圖片幻燈片

圖 9 闕值電壓和溝道長(zhǎng)度變化對(duì)SRAM設(shè)計(jì)的RAT, WAT和功耗的影響的仿真結(jié)果

下載: 全尺寸圖片幻燈片

圖 10 電壓0.8 V下的SNM比較

下載: 全尺寸圖片幻燈片

表 1 未加固/加固 SRAM 單元之間的可靠性和開(kāi)銷比較結(jié)果

SRAM	6T	NASA 13T	RHD 12T	QCCM 12T	QUCCE 12T	DNU SRM	We-Quatro	Yan 14T	QCCM 10T	RHSC 12T	SAR 14T	RHBD 10T	RHBD 12T
文獻(xiàn)	–	[18]	[19]	[20]	[21]	[22]	[23]	[25]	[20]	[26]	[27]	本文	本文
SNUR	×	×	√	×	×	√	×	×	×	√	√	√	√
#DHP	0	0	2	1	0	16	2	0	1	0	0	4	4
RAT (ps)	26.55	128.67	25.72	12.99	13.02	6.63	12.99	51.2	18.20	36.89	32.92	25.88	11.21
WAT (ps)	4.11	18.2	5.06	4.22	4.31	4.71	4.38	4.09	23.21	3.83	4.84	7.11	4.21
功耗(nW)	5.24	18.92	10.38	10.43	10.43	20.86	10.43	7.78	11.45	8.93	10.6	9.02	9.32
10^–3×面積(nm²)	4.35	9.07	8.27	8.71	8.71	17.42	8.71	10.25	7.79	8.71	12.44	7.30	8.71

下載: 導(dǎo)出CSV

參考文獻(xiàn)(30)

[1]	YAN Aibin, FAN Zhengzheng, DING Liang, et al. Cost-effective and highly reliable circuit-components design for safety-critical applications[J]. IEEE Transactions on Aerospace and Electronic Systems, 2022, 58(1): 517–529. doi: 10.1109/TAES.2021.3103586.
[2]	VACCA E, AZIMI S, DE SIO C, et al. Soft error reliability prediction of SRAM-based FPGA designs[C]. 2022 22nd European Conference on Radiation and Its Effects on Components and Systems (RADECS), Venice, Italy, 2022: 1–4. doi: 10.1109/RADECS55911.2022.10412546.
[3]	WANG Shida, TANG Min, ZHANG Hongwei, et al. Evaluation of single-event upset in FinFET device[C]. 2023 5th International Conference on Radiation Effects of Electronic Devices (ICREED), Kunming, China, 2023: 1–7. doi: 10.1109/ICREED59404.2023.10390726.
[4]	LIANG Huaguo, XU Xiumin, HUANG Zhengfeng, et al. A methodology for characterization of SET propagation in SRAM-based FPGAs[J]. IEEE Transactions on Nuclear Science, 2016, 63(6): 2985–2992. doi: 10.1109/TNS.2016.2620165.
[5]	BLACK J D, DODD P E, and WARREN K M. Physics of multiple-node charge collection and impacts on single-event characterization and soft error rate prediction[J]. IEEE Transactions on Nuclear Science, 2013, 60(3): 1836–1851. doi: 10.1109/TNS.2013.2260357.
[6]	YAN Aibin, XU Zhelong, FENG Xiangfeng, et al. Novel quadruple-node-upset-tolerant latch designs with optimized overhead for reliable computing in harsh radiation environments[J]. IEEE Transactions on Emerging Topics in Computing, 2022, 10(1): 404–413. doi: 10.1109/TETC.2020.3025584.
[7]	HATEFINASAB S, MEDINA-GARCIA A, MORALES D P, et al. Rule-based design for low-cost double-node upset tolerant self-recoverable D-Latch[J]. IEEE Access, 2023, 11: 1732–1741. doi: 10.1109/ACCESS.2022.3233812.
[8]	ZEINZINGER M, LANGER J, EIBENSTEINER F, et al. Comparative analysis of SRAM PUF temperature susceptibility on embedded systems[C]. 2023 International Conference on Electrical, Computer and Energy Technologies (ICECET), Cape Town, South Africa, 2023: 1–8. doi: 10.1109/ICECET58911.2023.10389242.
[9]	SUGITANI S, NAKAJIMA R, YOSHIDA K, et al. Radiation hardened flip-flops with low area, delay and power overheads in a 65 nm bulk process[C]. 2023 IEEE International Reliability Physics Symposium (IRPS), Monterey, USA, 2023: 1–5. doi: 10.1109/IRPS48203.2023.10117957.
[10]	YAN Aibin, LING Yafei, CUI Jie, et al. Quadruple cross-coupled dual-interlocked-storage-cells-based multiple-node-upset-tolerant latch designs[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(3): 879–890. doi: 10.1109/TCSI.2019.2959007.
[11]	TIAN Yuanxin, ZHANG Yuejun, ZHANG Huihong, et al. An architecture of a single-event tolerant D flip-flop using full-custom design in 28nm process[C]. 2023 IEEE 15th International Conference on ASIC (ASICON), Nanjing, China, 2023: 1–4. doi: 10.1109/ASICON58565.2023.10396468.
[12]	LAI Xiaoling, GUO Yangming, ZHANG Jian, et al. A novel circuit and layout design of SEU tolerant SRAM in a 65nm CMOS process[C]. 2023 IEEE 18th Conference on Industrial Electronics and Applications (ICIEA), Ningbo, China, 2023: 522–526. doi: 10.1109/ICIEA58696.2023.10241793.
[13]	JUNG I S, KIM Y B, and LOMBARDI F. A novel sort error hardened 10T SRAM cells for low voltage operation[C]. IEEE 55th International Midwest Symposium on Circuits and Systems, Boise, USA, 2012: 714–717. doi: 10.1109/MWSCAS.2012.6292120.
[14]	LIN Sheng, KIM Y B, and LOMBARDI F. Analysis and design of nanoscale CMOS storage elements for single-event hardening with multiple-node upset[J]. IEEE Transactions on Device and Materials Reliability, 2012, 12(1): 68–77. doi: 10.1109/TDMR.2011.2167233.
[15]	RAJAEI R, ASGARI B, TABANDEH M, et al. Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology[J]. Turkish Journal of Electrical Engineering and Computer Sciences, 2017, 25(2): 1035–1047. doi: 10.3906/elk-1502-124.
[16]	GUO Jing, ZHU Lei, SUN Yu, et al. Design of area-efficient and highly reliable RHBD 10T memory cell for aerospace applications[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(5): 991–994. doi: 10.1109/TVLSI.2017.2788439.
[17]	RAJAEI R, ASGARI B, TABANDEH M, et al. Design of robust SRAM cells against single-event multiple effects for nanometer technologies[J]. IEEE Transactions on Device and Materials Reliability, 2015, 15(3): 429–436. doi: 10.1109/TDMR.2015.2456832.
[18]	SHIYANOVSKII Y, RAJENDRAN A, and PAPACHRISTOU C. A low power memory cell design for SEU protection against radiation effects[C]. IEEE NASA/ESA Conference on Adaptive Hardware and Systems, Erlangen, Germany, 2012: 288–295. doi: 10.1109/AHS.2012.6268665.
[19]	QI Chunhua, XIAO Liyi, WANG Tianqi, et al. A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets[J]. IEEE Transactions on Device and Materials Reliability, 2016, 16(3): 388–395. doi: 10.1109/TDMR.2016.2593590.
[20]	YAN Aibin, ZHOU Jun, HU Yuanjie, et al. Novel quadruple cross-coupled memory cell designs with protection against single event upsets and double-node upsets[J]. IEEE Access, 2019, 7: 176188–176196. doi: 10.1109/access.2019.2958109.
[21]	JIANG Jianwei, XU Yiran, ZHU Wenyi, et al. Quadruple cross-coupled latch-based 10T and 12T SRAM bit-cell designs for highly reliable terrestrial applications[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(3): 967–977. doi: 10.1109/TCSI.2018.2872507.
[22]	YAN Aibin, WU Zhen, GUO Jing, et al. Novel double-node-upset-tolerant memory cell designs through radiation-hardening-by-design and layout[J]. IEEE Transactions on Reliability, 2019, 68(1): 354–363. doi: 10.1109/TR.2018.2876243.
[23]	DANG L D T, KIM J S, and CHANG I J. We-Quatro: Radiation-hardened SRAM cell with parametric process variation tolerance[J]. IEEE Transactions on Nuclear Science, 2017, 64(9): 2489–2496. doi: 10.1109/TNS.2017.2728180.
[24]	YAN Aibin, CHEN Yan, HU Yuanjie, et al. Novel speed-and-power-optimized SRAM cell designs with enhanced self-recoverability from single- and double-node upsets[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(12): 4684–4695. doi: 10.1109/TCSI.2020.3018328.
[25]	CHOUDHARY V and YADAV D S. Analysis of power, delay and SNM of 6T & 8T SRAM cells[C]. 2021 5th International Conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2021: 78–82. doi: 10.1109/ICECA52323.2021.9676022.
[26]	PRASAD G, MANDI B C, and ALI M. Design and analysis of 10T-boosted radiation hardened SRAM cell for aerospace applications[C]. 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Rourkela, India, 2019: 304–307. doi: 10.1109/iSES47678.2019.00075.
[27]	PAL S, MOHAPATRA S, KI W H, et al. Soft-error-aware read-decoupled SRAM WITH MULTI-NODE RECOVERY FOR AEROSPACE APPLICATions[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68(10): 3336–3340. doi: 10.1109/TCSII.2021.3073947.
[28]	董攀, 范隆, 岳素格, 等. 一種高溫單粒子效應(yīng)測(cè)試系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)[J]. 微電子學(xué)與計(jì)算機(jī), 2011, 28(12): 17–20,24. doi: 10.19304/j.cnki.issn1000-7180.2011.12.005. DONG Pan, FAN Long, YUE Suge, et al. A high temperature single event effects test system design and implementation[J]. Microelectronics & Computer, 2011, 28(12): 17–20,24. doi: 10.19304/j.cnki.issn1000-7180.2011.12.005.
[29]	劉冰燕, 蔡江錚, 黑勇. 應(yīng)用于超低電壓下的SRAM存儲(chǔ)單元設(shè)計(jì)[J]. 微電子學(xué)與計(jì)算機(jī), 2016, 33(9): 15–18,23. doi: 10.19304/j.cnki.issn1000-7180.2016.09.004. LIU Bingyan, CAI Jiangzheng, and HEI Yong. A SRAM bitcell design for ultra-low supply application[J]. Microelectronics & Computer, 2016, 33(9): 15–18,23. doi: 10.19304/j.cnki.issn1000-7180.2016.09.004.
[30]	PANDA S, KUMAR N M, and SARKAR C K. Power, delay and noise optimization of a SRAM cell using a different threshold voltages and high performance output noise reduction circuit[C]. 2009 4th International Conference on Computers and Devices for Communication (CODEC), Kolkata, India, 2009: 1–4.