面向深度神經(jīng)網(wǎng)絡(luò)加速芯片的高效硬件優(yōu)化策略
doi: 10.11999/JEIT210002
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東南大學(xué)電子學(xué)院國家專用集成電路系統(tǒng)工程技術(shù)研究中心 南京 210096
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復(fù)旦大學(xué)專用集成電路與系統(tǒng)國家重點(diǎn)實(shí)驗(yàn)室 上海 200433
Efficient Hardware Optimization Strategies for Deep Neural Networks Acceleration Chip
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National ASIC Engineering Center, School of Electronic Sci. and Eng., Southeast University, Nanjing 210096, China
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National ASIC Key Laboratory, Fudan University, Shanghai 200433, China
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摘要: 輕量級神經(jīng)網(wǎng)絡(luò)部署在低功耗平臺(tái)上的解決方案可有效用于無人機(jī)(UAV)檢測、自動(dòng)駕駛等人工智能(AI)、物聯(lián)網(wǎng)(IOT)領(lǐng)域,但在資源有限情況下,同時(shí)兼顧高精度和低延時(shí)來構(gòu)建深度神經(jīng)網(wǎng)絡(luò)(DNN)加速器是非常有挑戰(zhàn)性的。該文針對此問題提出一系列高效的硬件優(yōu)化策略,包括構(gòu)建可堆疊共享計(jì)算引擎(PE)以平衡不同卷積中數(shù)據(jù)重用和內(nèi)存訪問模式的不一致;提出了可調(diào)的循環(huán)次數(shù)和通道增強(qiáng)方法,有效擴(kuò)展加速器與外部存儲(chǔ)器之間的訪問帶寬,提高DNN淺層網(wǎng)絡(luò)計(jì)算效率;優(yōu)化了預(yù)加載工作流,從整體上提高了異構(gòu)系統(tǒng)的并行度。經(jīng)Xilinx Ultra96 V2板卡驗(yàn)證,該文的硬件優(yōu)化策略有效地改進(jìn)了iSmart3-SkyNet和SkrSkr-SkyNet類的DNN加速芯片設(shè)計(jì)。結(jié)果顯示,優(yōu)化后的加速器每秒處理78.576幀圖像,每幅圖像的功耗為0.068 J。
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關(guān)鍵詞:
- 深度神經(jīng)網(wǎng)絡(luò) /
- 目標(biāo)檢測 /
- 神經(jīng)網(wǎng)絡(luò)加速器 /
- 低功耗 /
- 硬件優(yōu)化
Abstract: Lightweight neural networks deployed on low-power platforms have proven to be effective solutions for Artificial Intelligence (AI) and Internet Of Things (IOT) domains such as Unmanned Aerial Vehicle (UAV) detection and unmanned driving. However, in the case of limited resources, it is very challenging to build Deep Neural Networks (DNN) accelerator with both high precision and low delay. In this paper, a series of efficient hardware optimization strategies are proposed, including stackable shared Processing Engine (PE) to balance the inconsistency of data reuse and memory access patterns in different convolutions; Regulable loop parallelism and channel augmentation are proposed to increase effectively the access bandwidth between accelerator and external memory. It also improve the efficiency of DNN shallow layers computing; Pre-Workflow is applied to improve the overall parallelism of heterogeneous systems. Verified by Xilinx Ultra96 V2 board, the hardware optimization strategies in this paper improve effectively the design of DNN acceleration chips like iSmart3-SkyNet and SkrSkr-SkyNet. The results show that the optimized accelerator processes 78.576 frames per second, and the power consumption of each picture is 0.068 Joules. -
表 1 SkyNet的體系結(jié)構(gòu)和每個(gè)捆綁包的推理速度表格
捆綁包 層數(shù) 輸入尺寸 操作類型 計(jì)算量、計(jì)算量占比(%) 延遲占比(%) #1 1 3×160×320 DW-Conv3 119.61M, 20.6 33.90 2 3×160×320 PW-Conv1 3 48×160×320 POOLING #2 4 48×80×160 DW-Conv3 86.02M, 14.42 16.54 5 48×80×160 PW-Conv1 6 96×80×160 POOLING #3 7 96×40×80 DW-Conv3 61.75M, 10.36 6.23 8 96×40×80 PW-Conv1 9 192×40×80 POOLING #4 10 192×20×40 DW-Conv3 60.36M, 10.13 4.92 11 192×20×40 PW-Conv1 #5 12 384×20×40 DW-Conv3 160.05M, 26.85 12.43 13 384×20×40 PW-Conv1 #6 – 合并第9層輸出 107.52M, 18.04 20.08 14 1280×20×40 [旁路] DW-Conv3 15 1280×20×40 PW-Conv1 #7 16 96×20×40 PW-Conv1 0.77M, 0.14 0.10 – 17 10×20×40 計(jì)算回歸框 0.16 CPU – – – – 5.64 下載: 導(dǎo)出CSV
表 2 優(yōu)化策略效果對比
加速器 iSmart3 [9] SEUer A Skrskr [10] SEUer B 網(wǎng)絡(luò)模型 SkyNet SkyNet SkyNet SkyNet 量化精度 A9/W11 A9/W11 A8/W6 A8/W6 硬件平臺(tái) Ultra96V2 Ultra96V2 Ultra96V2 Ultra96V2 準(zhǔn)確率(DJI) 0.716 0.724 0.731 0.731 時(shí)鐘頻率(MHz) 215 215 300 300 DSP數(shù)量 329 287 360 360 LUT數(shù)量(k) 54 54 56 46 FF數(shù)量(k) 60 70 68 51 幀率(fps) 25.05 37.393 52.429 78.576 GOPS/W 3.21 5.95 7.22 11.19 Energy/Pic.(J) 0.289 0.135 0.129 0.068 下載: 導(dǎo)出CSV
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