一種通用的時(shí)間數(shù)字轉(zhuǎn)換器碼密度校準(zhǔn)信號(hào)產(chǎn)生方法及其實(shí)現(xiàn)
doi: 10.11999/JEIT200769
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強(qiáng)脈沖輻射環(huán)境模擬與效應(yīng)國(guó)家重點(diǎn)實(shí)驗(yàn)室 西安 710024
A General Method of Generating Code Density Calibration Signal for Time-to-Digital Converter and Its Realization
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State Key Laboratory of Intense Pulsed Radiation Simulation and Effect, Xi’an 710024, China
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摘要: 該文提出一種通用的時(shí)間數(shù)字轉(zhuǎn)換器(TDC)碼密度校準(zhǔn)信號(hào)產(chǎn)生方法，該方法基于相干采樣理論，通過(guò)合理設(shè)置TDC主時(shí)鐘和校準(zhǔn)信號(hào)之間的頻率差，結(jié)合輸出信號(hào)保持電路，產(chǎn)生校準(zhǔn)用的隨機(jī)信號(hào)，在碼密度校準(zhǔn)過(guò)程中，隨機(jī)信號(hào)均勻分布在TDC的延時(shí)路徑上，實(shí)現(xiàn)對(duì)TDC的bin-by-bin校準(zhǔn)?；赬ilinx公司的28 nm工藝的Kintex-7 現(xiàn)場(chǎng)可編程門陣列(FPGA)內(nèi)部的進(jìn)位鏈實(shí)現(xiàn)一種plain TDC，利用該方法校準(zhǔn)plain TDC的碼寬(抽頭延遲時(shí)間)，研究校準(zhǔn)了2抽頭方式下的TDC的性能參數(shù)，時(shí)間分辨率(對(duì)應(yīng)TDC的最低有效位，Least Significant Bit, LSB)為24.9 ps，微分非線性為(–0.84～3.1)LSB，積分非線性為(–5.0～2.2)LSB。文中所述的校準(zhǔn)方法采用時(shí)鐘邏輯資源實(shí)現(xiàn)，多次測(cè)試考核結(jié)果表明，單個(gè)延時(shí)單元的標(biāo)準(zhǔn)差優(yōu)于0.5 ps。該校準(zhǔn)方法采用時(shí)鐘邏輯資源代替組合邏輯資源，重復(fù)性、穩(wěn)定性較好，實(shí)現(xiàn)了對(duì)plain TDC的高精度自動(dòng)校準(zhǔn)。該方法同樣適用于其他類型的TDC的碼密度校準(zhǔn)。
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關(guān)鍵詞:
- 時(shí)間數(shù)字轉(zhuǎn)換器 /
- 碼密度校準(zhǔn) /
- 相干采樣 /
- TDC主時(shí)鐘 /
- 校準(zhǔn)信號(hào)
Abstract: This paper proposes a universal Time-to-Digital Converter (TDC) code density calibration signal generation method, which is based on the theory of coherent sampling. By reasonably setting the frequency difference between the TDC master clock and the calibration signal, combining with the output hold circuit, a random signal for calibration is generated to ensure that the random signal is evenly distributed on the TDC delay path to achieve Bin-by-bin calibration of TDC. The paper implements a carry chain plain TDC based on XILINX’s 28 nm Kintex-7 Field Programmable Gate Array (FPGA). The method is used to calibrate the code width (tap delay time) of plain TDC, and the performance parameters of TDC in 2-tap mode are studied and calibrated. The time resolution (corresponding to the least significant bit of TDC, Least Significant Bit, LSB) is 24.9 ps, with the differential nonlinearity is (–0.84～3.1) LSB, and the integral nonlinearity is (–5.0～2.2) LSB. The calibration method described in the paper is implemented using clock logic resources, and multiple tests show that the standard deviation of a single delay unit is better than 0.5 ps. This calibration method uses clock logic resources instead of combinatorial logic resources to realize high-precision automatic calibration of plain TDC, with good repeatability and stability. This method is also suitable for other types of TDC code density calibration. -
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