一種低功耗高噪聲源真隨機(jī)數(shù)設(shè)計(jì)

魏子魁; 胡毅; 金鑫; 李振國(guó); 馮文楠; 馮曦; 唐曉柯

doi:10.11999/JEIT190719

一種低功耗高噪聲源真隨機(jī)數(shù)設(shè)計(jì)

doi: 10.11999/JEIT190719

1.
北京智芯微電子科技有限公司國(guó)家電網(wǎng)公司重點(diǎn)實(shí)驗(yàn)室電力芯片設(shè)計(jì)分析實(shí)驗(yàn)室北京 100192
2.
北京智芯微電子科技有限公司北京市電力高可靠性集成電路設(shè)計(jì)工程技術(shù)研究中心北京 100192

基金項(xiàng)目: 國(guó)家核高基重大專項(xiàng)(2017ZX01030204)

詳細(xì)信息

作者簡(jiǎn)介:
魏子魁：男，1989年生，工程師，研究方向?yàn)槟M集成電路設(shè)計(jì)和測(cè)試

胡毅：男，1982年生，工程師，研究方向?yàn)槟M集成電路設(shè)計(jì)和芯片技術(shù)

金鑫：女，1987年生，工程師，研究方向?yàn)槟M集成電路設(shè)計(jì)

通訊作者:
魏子魁　weizikui@sgitg.sgcc.com.cn

中圖分類號(hào): TN47
計(jì)量
- 文章訪問(wèn)數(shù): 2624
- HTML全文瀏覽量: 1265
- PDF下載量: 113
- 被引次數(shù): 0
出版歷程
- 收稿日期: 2019-08-29
- 修回日期: 2020-03-04
- 網(wǎng)絡(luò)出版日期: 2020-03-31
- 刊出日期: 2020-10-13

A True Random Number Design of Low Power and High Noise Source

1.
State Grid Key Laboratory of Power Industrial Chip Design and Analysis Technology, Beijing Smart-Chip Microelectronics Technology Co. Ltd., Beijing 100192, China
2.
Beijing Engineering Research Center of High-reliability IC with Power Industrial Grade, Beijing Smart-Chip Microelectronics Technology Co. Ltd., Beijing 100192, China

Funds: The Core Electronic Devices, High-end Generic Chips and Basic Software Major Project (2017ZX01030204)

摘要

摘要: 通過(guò)對(duì)一種低功耗高噪聲源真隨機(jī)數(shù)發(fā)生器(TRNG)的研究，設(shè)計(jì)了一種新型的低頻時(shí)鐘電路，可以把電阻熱噪聲放大100倍以上，從而減少低頻時(shí)鐘電路的帶寬和電阻值，使電路的面積和功耗減少，并且使低頻時(shí)鐘的jitter到達(dá)58.2 ns。電路采用SMIC 40 nm CMOS工藝設(shè)計(jì)，完成了流片和測(cè)試，真隨機(jī)數(shù)產(chǎn)生器輸出速度范圍為1.38～3.33 Mbit/s，電路整體功耗為0.11 mW，面積為0.00789 mm²。隨機(jī)數(shù)輸出滿足AIS31真隨機(jī)數(shù)熵源測(cè)試要求，并且通過(guò)了國(guó)密2安全測(cè)試。
- 真隨機(jī)數(shù)產(chǎn)生器 /
- 電阻熱噪聲 /
- 低頻時(shí)鐘jitter /
- 低功耗
Abstract: Through the research of a True Random Number Generator (TRNG), which is a low-power and high-noise source, a new type of low-frequency clock is designed. It can amplify the thermal noise of resistance more than 100 times, thus reducing the bandwidth and resistance value of the circuit, reducing the area and power consumption of the circuit, and making the jitter of low-frequency clock reach 58.2 ns. The circuit is designed by SMIC 40 nm CMOS technology. The flow sheet and test are completed. The output speed of TRNG ranges from 1.38 to 3.33 Mbit/s. The overall power consumption of the circuit is 0.11 mW and the area is 0.00789 mm². The output of random number meets the test requirement of AIS31 true random number entropy source, and passes the security test of National Secret 2.
- True Random Number Generator (TRNG) /
- Resistance thermal noise /
- Low-frequency oscillator jitter /
- Low power consumption

HTML全文

圖 1 真隨機(jī)數(shù)發(fā)生器結(jié)構(gòu)

下載: 全尺寸圖片幻燈片

圖 2 低頻時(shí)鐘電路圖

下載: 全尺寸圖片幻燈片

圖 3 帶噪聲的三角波

下載: 全尺寸圖片幻燈片

圖 4 普通電壓放大器放大電阻噪聲原理圖

下載: 全尺寸圖片幻燈片

圖 5 低頻時(shí)鐘輸出jitter

下載: 全尺寸圖片幻燈片

圖 6 低頻時(shí)鐘jitter的正態(tài)分布情況

下載: 全尺寸圖片幻燈片

圖 7 整體電路版圖

下載: 全尺寸圖片幻燈片

表 1 兩種結(jié)構(gòu)下噪聲電阻值和功耗

指標(biāo)	噪聲電阻值 (Ω)	信號(hào)增益A₁(倍)	信號(hào)增益A₂(倍)	噪聲帶寬(MHz)	功耗(mW)
跨阻放大器結(jié)構(gòu)	64 k	1	100	1	0.081
電壓放大器結(jié)構(gòu)	2 M	5	5	80	0.220

下載: 導(dǎo)出CSV

表 2 低頻時(shí)鐘頻率仿真結(jié)果

指標(biāo)	仿真結(jié)果
指標(biāo)	MIN	TYP	MAX
輸出頻率(MHz)	1.38	2.13	3.34
Jitter(σ{T_cl})(ns)	77.89	58.2	40
功耗(mW)	0.055	0.081	0.110

下載: 導(dǎo)出CSV

表 3 高頻時(shí)鐘頻率仿真結(jié)果

仿真	HOSC頻率
仿真	MIN	TYP	MAX
頻率(GHz)	0.186	0.25	0.313
功耗(mW)	0.017	0.024	0.035
占空比(%)	50.09	50.28	50.43

下載: 導(dǎo)出CSV

表 4 幾種不同TRNG 性能比較

方法	基本原理	工藝(nm)	功耗(mW)	速度(Mbit/s)	面積(mm²)	S(mW·mm²·s/Mbit)
文獻(xiàn)[15]	相位抖動(dòng)	28	0.54	23	0.0375	0.88
文獻(xiàn)[8]	相位抖動(dòng)	130	0.04	0.1	0.005	2
文獻(xiàn)[10]	熱噪聲	28	0.388	4	0.025	2.43
文獻(xiàn)[16]	熱噪聲	55	0.81	10	0.0124	1
本文	熱噪聲	40	0.11	2	0.0079	0.44

下載: 導(dǎo)出CSV

參考文獻(xiàn)(16)

蘇桂平, 呂述望, 楊柱, 等. 真隨機(jī)數(shù)發(fā)生器的隨機(jī)性在信息安全中的應(yīng)用[J]. 計(jì)算機(jī)工程, 2002, 28(6): 114–115. doi: 10.3969/j.issn.1000-3428.2002.06.044

SU Guiping, Lü Shuwang, YANG Zhu, et al. Application of the randomness of a random number generator in the information security[J]. Computer Engineering, 2002, 28(6): 114–115. doi: 10.3969/j.issn.1000-3428.2002.06.044

張仿. 隨機(jī)數(shù)在加密技術(shù)中的應(yīng)用分析[J]. 計(jì)算機(jī)應(yīng)用與軟件, 2004, 21(12): 105–107. doi: 10.3969/j.issn.1000-386X.2004.12.041

ZHANG Fang. Analysis and application of random number in encryption[J]. Computer Applications and Software, 2004, 21(12): 105–107. doi: 10.3969/j.issn.1000-386X.2004.12.041

張玉浩, 徐志鵬, 黃新銳, 等. 基于AES加密電路的防復(fù)制電路及系統(tǒng)設(shè)計(jì)[J]. 電子器件, 2015, 38(1): 103–107. doi: 10.3969/j.issn.1005-9490.2015.01.023

ZHANG Yuhao, XU Zhipeng, HUANG Xinrui, et al. Design of copy prevention circuit and system based on AES encryption circuit[J]. Chinese Journal of Electron Devices, 2015, 38(1): 103–107. doi: 10.3969/j.issn.1005-9490.2015.01.023

馬原, 陳天宇, 吳鑫瑩, 等. 隨機(jī)數(shù)發(fā)生器的設(shè)計(jì)與檢測(cè)[J]. 信息安全研究, 2019, 5(1): 39–49. doi: 10.3969/j.issn.2096-1057.2019.01.005

MA Yuan, CHEN Tianyu, WU Xinying, et al. Design, implementation and testing of random number generators[J]. Journal of Information Security Research, 2019, 5(1): 39–49. doi: 10.3969/j.issn.2096-1057.2019.01.005

WIECZOREK P Z. Lightweight TRNG based on multiphase timing of bistables[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2016, 63(7): 1043–1054. doi: 10.1109/TCSI.2016.2555248

臧鴻雁, 李玖, 李國(guó)東. 一個(gè)一維離散混沌判定定理及其在偽隨機(jī)數(shù)發(fā)生器中的應(yīng)用[J]. 電子與信息學(xué)報(bào), 2018, 40(8): 1992–1997. doi: 10.11999/JEIT171139

ZANG Hongyan, LI Jiu, and LI Guodong. A one-dimensional discrete map chaos criterion theorem with applications in pseudo-random number generator[J]. Journal of Electronics &Information Technology, 2018, 40(8): 1992–1997. doi: 10.11999/JEIT171139

PARESCHI F, SETTI G, and ROVATTI R. A fast chaos-based true random number generator for cryptographic applications[C]. The 32nd European Solid-State Circuits Conference, Montreux, Switzerland, 2006: 130–133. doi: 10.1109/ESSCIR.2006.307548.

LIU Dongsheng, LIU Zilong, LI Lun, et al. A low-cost low-power ring oscillator-based truly random number generator for encryption on smart cards[J]. IEEE Transactions on Circuits and Systems Ⅱ: Express Briefs, 2016, 63(6): 608–612. doi: 10.1109/TCSⅡ.2016.2530800

李冰, 徐云晶, 陳帥, 等. 基于SRAM物理不可克隆函數(shù)的高效真隨機(jī)種子發(fā)生器設(shè)計(jì)[J]. 電子與信息學(xué)報(bào), 2017, 39(6): 1458–1463. doi: 10.11999/JEIT160835

LI Bing, XU Yunjing, CHEN Shuai, et al. Efficient design of truly random seed generator based on SRAM physical unclonable functions[J]. Journal of Electronics &Information Technology, 2017, 39(6): 1458–1463. doi: 10.11999/JEIT160835

魏子魁, 符令, 王雪, 等. 一種基于熱噪聲振蕩器的高速真隨機(jī)數(shù)設(shè)計(jì)[J]. 電子技術(shù)應(yīng)用, 2018, 44(10): 29–31, 36. doi: 10.16157/j.issn.0258-7998.180002

WEI Zikui, FU Ling, WANG Xue, et al. A high speed truly random number generator based on thermal noise oscilltor[J]. Application of Electronic Technique, 2018, 44(10): 29–31, 36. doi: 10.16157/j.issn.0258-7998.180002

葉少康, 李崢. 基于數(shù)?；旌系恼骐S機(jī)數(shù)發(fā)生器[J]. 計(jì)算機(jī)工程與設(shè)計(jì), 2012, 33(4): 1602–1606, 1622. doi: 10.16208/j.issn1000-7024.2012.04.017

YE Shaokang and LI Zheng. True random number generator based on mixed-signal circuit[J]. Computer Engineering and Design, 2012, 33(4): 1602–1606, 1622. doi: 10.16208/j.issn1000-7024.2012.04.017

王浩宇, 梁華國(guó), 徐秀敏, 等. 一種基于FPGA的Latch結(jié)構(gòu)真隨機(jī)數(shù)發(fā)生器[J]. 微電子學(xué), 2018, 48(5): 635–641. doi: 10.13911/j.cnki.1004-3365.170532

WANG Haoyu, LIANG Huaguo, XU Xiuming, et al. A latch structure true random number generator based on FPGA[J]. Microelectronics, 2018, 48(5): 635–641. doi: 10.13911/j.cnki.1004-3365.170532

LIU Yao, CHEUNG R C C, and WONG H. A bias-bounded digital true random number generator architecture[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, 64(1): 133–144. doi: 10.1109/TCSI.2016.2606353

辛可為, 呂方旭, 王建業(yè), 等. 適用于4通道100 Gbps SerDes的兩級(jí)架構(gòu)正交12.5 GHz低功耗低抖動(dòng)時(shí)鐘發(fā)生器[J]. 空軍工程大學(xué)學(xué)報(bào): 自然科學(xué)版, 2019, 20(5): 64–69.

XIN Kewei, Lü Fangxu, WANG Jianye, et al. A 12.5 GHz clock generator applicable for 4 way 100 Gbps high speed serial interface circuits[J]. Journal of Air Force Engineering University:Natural Science Edition, 2019, 20(5): 64–69.

YANG Kaiyuan, FICK D, HENRY M B, et al. 16.3 A 23Mb/s 23pJ/b fully synthesized true-random-number generator in 28nm and 65nm CMOS[C]. 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, USA, 2014: 280-281. doi: 10.1109/ISSCC.2014.6757434.

王鵬君, 李楨, 李剛, 等. 基于壓控振蕩器的真隨機(jī)數(shù)發(fā)生器設(shè)計(jì)[J]. 電子學(xué)報(bào), 2019, 47(2): 417–421. doi: 10.3969/j.issn.0372-2112.2019.02.022

WANG Pengjun, LI Zhen, LI Gang, et al. Design of true random number generator based on VCO[J]. Acta Electronica Sinica, 2019, 47(2): 417–421. doi: 10.3969/j.issn.0372-2112.2019.02.022

相關(guān)文章

施引文獻(xiàn)

資源附件(0)

訪問(wèn)統(tǒng)計(jì)