用于14位210 MS/s電荷域ADC的4.5位子級電路

薛顏; 于宗光; 陳珍海; 魏敬和; 錢宏文

doi:10.11999/JEIT190592

用于14位210 MS/s電荷域ADC的4.5位子級電路

doi: 10.11999/JEIT190592

薛顏¹,
于宗光^1, ,,
陳珍海^{1, 2, 3},
魏敬和¹,
錢宏文¹

1.
中國電子科技集團第五十八研究所無錫 214035
2.
黃山學(xué)院信息工程學(xué)院黃山 245041
3.
智能微系統(tǒng)安徽省工程技術(shù)研究中心黃山 245041

詳細信息

作者簡介:
薛顏：男，1983年生，工程師，研究方向為物理電子學(xué)

于宗光：男，1964年生，教授，研究方向為微電子學(xué)

陳珍海：男，1982年生，高級工程師，研究方向為微電子學(xué)與固體電子學(xué)

魏敬和：男，1970年生，研究員，研究方向為集成電路設(shè)計

錢宏文：男，1975年生，研究員，研究方向為集成電路應(yīng)用

通訊作者:
于宗光　yuzg58@163.com

中圖分類號: TN47
計量
- 文章訪問數(shù): 1211
- HTML全文瀏覽量: 739
- PDF下載量: 53
- 被引次數(shù): 0
出版歷程
- 收稿日期: 2019-08-06
- 修回日期: 2020-08-06
- 網(wǎng)絡(luò)出版日期: 2020-08-12
- 刊出日期: 2020-09-27

4.5 bit Sub-stage Circuit for 14 bit 210 MS/s Charge-domain ADC

Yan XUE¹,
Zongguang YU^{1
, ,},
Zhenhai CHEN^{1, 2, 3},
Jinghe WEI¹,
Hongwen QIAN¹

1.
No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi 214035, China
2.
School of Information Engineering, Huangshan University, Huangshan 245041, China
3.
Engineering Technology Research Center of Intelligent Microsystems AnHui Province, Huangshan 245041, China

摘要

摘要: 該文提出了一種用于高速高精度電荷域流水線模數(shù)轉(zhuǎn)換器(ADC)的電荷域4.5位前端子級電路。該4.5位子級電路使用增強型電荷傳輸(BCT)電路替代傳統(tǒng)開關(guān)電容技術(shù)流水線ADC中的高增益帶寬積運放來實現(xiàn)電荷信號傳輸和余量處理，從而實現(xiàn)超低功耗。所提4.5位子級電路被運用于一款14位210 MS/s電荷域ADC中作為前端第1級子級電路，并在1P6M 0.18 μm CMOS工藝下實現(xiàn)。測試結(jié)果顯示，該14位ADC電路在210 MS/s條件下對于30.1 MHz單音正弦輸入信號得到的無雜散動態(tài)范圍為85.4 dBc，信噪比為71.5 dBFS, ADC內(nèi)核面積為3.2 mm²，功耗僅為205 mW。
- 流水線模數(shù)轉(zhuǎn)換器 /
- 電荷域 /
- 子級電路 /
- 低功耗
Abstract: A 4.5 bit sub-stage circuit for high speed high precision charge domain pipelined Analog-to-Digital Converter (ADC) is proposed. Instead of the high-performance opamps used in traditional switched-capacitor pipelined ADCs, charge transfer and residue charge calculation is realized with Boosted Charge Transfer (BCT) circuit in the proposed 4.5 bit sub-stage. Therefore, the power consumption of the 4.5 bit sub-stage circuit can be reduced remarkably. The proposed 4.5 bit sub-stage circuit is used as the 1st stage circuit for a 14 bit 210 MS/s charge domain pipelined ADC and realized in a 1P6M 0.18 μm CMOS process. Test results show the 14 bit 210 MS/s ADC achieves the signal-to-noise ratio of 71.5 dBFS and the spurious free dynamic range of 85.4 dB, with 30.1 MHz input single tone signal at 210 MS/s, while the ADC core consumes the power consumption of 205 mW and occupies an area of 3.2 mm².
- Pipelined Analog-to-Digital Converter(ADC) /
- Charge-domain /
- Sub-stage circuit /
- Low power

HTML全文

圖 1 電荷域4.5位每級子級結(jié)構(gòu)

下載: 全尺寸圖片幻燈片

圖 2 鏡像控制BCT電路結(jié)構(gòu)

下載: 全尺寸圖片幻燈片

圖 3 高速動態(tài)電荷比較器電路結(jié)構(gòu)

下載: 全尺寸圖片幻燈片

圖 4 4.5位子級電路仿真曲線

下載: 全尺寸圖片幻燈片

圖 5 14位210 MS/s電荷域ADC框圖及芯片照片

下載: 全尺寸圖片幻燈片

圖 6 ADC實測FFT結(jié)果

下載: 全尺寸圖片幻燈片

表 1 本電路部分關(guān)鍵實測數(shù)據(jù)

測試電路	精度(bit)	輸入信號(MHz)	采樣率(MS/s)	溫度(°C)	SNR(dB)	SFDR(dB)	內(nèi)核電流(mA)	內(nèi)核功耗(mW)
電路1	14	30.1	210	–40	68.3	80.2	109	197
				25	71. 5	85.4	114	205
				85	71.3	83.6	119	214
電路2	14	30.1	210	–40	68.1	79.8	108	194
				25	71.4	85.2	113	203
				85	71.1	83.2	117	211

下載: 導(dǎo)出CSV

表 2 ADC性能對比

技術(shù)指標	精度 (bit)	采樣率 (MS/s)	SNR (dB)	SFDR (dB)	電源電壓 (V)	工藝 (nm)	內(nèi)核功耗 (mW)	內(nèi)核面積 (mm²)	FOM(pJ/step)功耗/ (2^ENOB·f_clk)
文獻[4]	14	500	64.8	92.7	1.8/3.3	180	550	2.5*	0.71
文獻[5]	14	1000	69	86	1.2/2.5	65	1200	5	0.55
文獻[14]	14	200	68.5	88.5	1.8	180	460	22.5**	1.07
文獻[15]	14	250	68.5	94.7	1.8	180	300	3.6	0.57
本文	14	210	71.5	85.4	1.8	180	205	3.2	0.39
注：采用SiGe BiCMOS工藝；*采用時間交織結(jié)構(gòu)。

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