基于公式遞推法的可變計(jì)算位寬的循環(huán)冗余校驗(yàn)設(shè)計(jì)與實(shí)現(xiàn)
doi: 10.11999/JEIT190503
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中國科學(xué)院微電子研究所 北京 100029
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中國科學(xué)院大學(xué) 北京 100049
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三維及納米集成電路設(shè)計(jì)自動(dòng)化技術(shù)北京市重點(diǎn)實(shí)驗(yàn)室 北京 100029
Design and Implementation of Cyclic Redundancy Check with Variable Computing Width Based on Formula Recursive Algorithm
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1.
Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
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University of Chinese Academy of Sciences, Beijing 100049, China
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Beijing Key Laboratory of Three-dimensional and Nanometer Integrated Circuit Design Automation Technology, Beijing 100029, China
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摘要:
循環(huán)冗余校驗(yàn)(CRC)與信道編碼的級聯(lián)使用，可以有效改善譯碼的收斂特性。在新一代無線通信系統(tǒng)，如5G中，碼長和碼率都具有多樣性。為了提高編譯碼分段長度可變的級聯(lián)系統(tǒng)的譯碼效率，該文提出一種可變計(jì)算位寬的CRC并行算法。該算法在現(xiàn)有固定位寬并行算法的基礎(chǔ)上，合并公式遞推法中反饋數(shù)據(jù)與輸入數(shù)據(jù)的并行計(jì)算，實(shí)現(xiàn)了一種高并行度的CRC校驗(yàn)架構(gòu)，并且支持可變位寬的CRC計(jì)算。與現(xiàn)有的并行算法相比，合并算法節(jié)省了電路資源的開銷，在位寬固定時(shí)，資源節(jié)約效果明顯，同時(shí)在反饋時(shí)延上也有將近50%的優(yōu)化；在位寬可變時(shí)，電路資源的使用情況也有相應(yīng)的優(yōu)化。
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關(guān)鍵詞:
- 循環(huán)冗余校驗(yàn) /
- 并行算法 /
- 公式遞推法
Abstract:Cyclic Redundancy Check (CRC) is used in cascade with channel coding to improve the convergence of the decoding. In the new generation of wireless communication systems, such as 5G, both code length and code rate are diverse. To improve the decoding efficiency of cascaded systems, a CRC parallel algorithm with variable computing width is proposed in this paper. Based on the existing fixed bit-width parallel algorithm, this algorithm combines the parallel calculation of feedback data and input data in the formula recursive method, realizing a highly parallel CRC check architecture with variable bit-width CRC calculation. Compared with the existing parallel algorithms, the merged algorithm saves the overhead of circuit resources. When the bit-width is fixed, the resource saving effect is obvious, and at the same time, the feedback delay is also optimized by nearly 50%. When the bit-width is variable, the use of resources is also optimized accordingly.
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表 1 硬件資源開銷
項(xiàng)目 值 頂層實(shí)體名 crc_24 芯片 EP3C5E144C7(Cyclone III) 邏輯器件數(shù) 434/5136(8%) 寄存器數(shù) 26 管腳數(shù) 68/95(72%) 
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表 2 仿真測試結(jié)果
總長度
(bit)Num Matlab結(jié)果 仿真結(jié)果 數(shù)據(jù)1 60 7, 24, 29 001111010110111111110110 24’h3d6ff6 數(shù)據(jù)2 65 23, 32, 10 001110000010011011010001 24’h3826d1 數(shù)據(jù)3 70 24, 15, 31 011111100000011111011011 24’h7e07db
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表 3 選用的生成多項(xiàng)式
CRC 生成多項(xiàng)式 CRC-12 ${x^{12}} + {x^{11}} + {x^3} + {x^2} + x + 1$ CRC-16 ${x^{16}} + {x^{15}} + {x^2} + 1$ CRC-32 $\begin{array}{l}{x^{32}} + {x^{26}} + {x^{23}} + {x^{22}} + {x^{16}} + {x^{12}} + {x^{11}} + \\{x^{10}} + {x^8} + {x^7} + {x^5} + {x^4} + {x^2} + x + 1\end{array}$
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表 4 電路資源和關(guān)鍵路徑長度比較
CRC式子(M=r) 算法 總計(jì) 1 異或 關(guān)鍵路徑 CRC-12(12) 文獻(xiàn)[7] 136 112 9 文獻(xiàn)[8] 120 66 8 文獻(xiàn)[10] – 103 8 文獻(xiàn)[9] 77 53 8 固定 52 43 5 可變 64 78 9 CRC-16(16) 文獻(xiàn)[7] 218 186 10 文獻(xiàn)[8] 188 98 10 文獻(xiàn)[10] – 94 10 文獻(xiàn)[9] 100 60 9 固定 72 54 5 可變 88 101 9 CRC-32(32) 文獻(xiàn)[7] 1031 967 12 文獻(xiàn)[8] 928 518 12 文獻(xiàn)[10] – 675 10 文獻(xiàn)[9] 888 461 12 固定 452 313 6 可變 484 408 11
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