基于配置模式匹配和層次化映射結(jié)構的高效FPGA碼流生成系統(tǒng)研究
doi: 10.11999/JEIT190143
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1.
中國科學院電子學研究所 北京 100190
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2.
中國科學院大學 北京 100049
Research on Efficient FPGA Bitstream Generation System Based on Mode Matching and Hierarchical Mapping
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1.
Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
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2.
University of Chinese Academy of Sciences, Beijing 100049, China
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摘要: 碼流生成在FPGA電子設計自動化(EDA)流程中,提供應用電路在芯片上物理實現(xiàn)所需的精準配置信息。現(xiàn)代FPGA的發(fā)展一方面呈現(xiàn)出器件規(guī)模及碼流容量越來越大的趨勢,另一方面越來越多可變陣列大小的嵌入式應用(例如eFPGA)又要求碼流生成器具備更高的配置效率以及更精簡的可重構數(shù)據(jù)庫。針對碼流生成時間增加的問題和陣列規(guī)模任意縮放的需求,該文提出一種模式匹配和層次映射的碼流生成方法,即對編程單元按配置模式進行分類建模,在配置時按模型進行調(diào)用匹配,并采用了層次化的碼流映射策略,使得數(shù)據(jù)庫可隨陣列排布調(diào)整動態(tài)生成。該方法可有效應對FPGA嵌入式應用中碼流容量的增大以及陣列規(guī)模可變所帶來的挑戰(zhàn),同時相比平面化的建模及映射方法,碼流配置的時間復雜度由O(n)降低為O(lgn)。Abstract: Bitstream generator in FPGA Electronic Design Automation(EDA) offers precise configuration information, which enables the application circuits to be implemented on the target device. On one hand, modern FPGAs tend to have larger device scale and more configuration bits, on the other hand, embedded applications (e.g. eFPGAs) require better configuration efficiency and smaller, more adaptive database. In order to meet these new requirements, a bit-stream generation method is proposed which firstly models the configurable resources by configuration modes and matches the netlist with these models, then hierarchical mapping strategy is used to search every bit on a dynamically generated database determined by the array floorplan. This method well meets the challenges that embedded applications may bring-the surge of configuration bit count and the changeable size of the array. Compared to flattened modelling and mapping method, its time complexity is reduced from O(n) to O(lgn).
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Key words:
- FPGA /
- Bitstream generation /
- Embedded /
- Configuration mode /
- Hierarchy
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表 1 芯片相關數(shù)據(jù)庫大小(kB)
器件模型* config_modes tile/primitive_first_addresses initial_bitstream bitstream_format_info 數(shù)據(jù)庫總大小(kB) 器件a(3 M Gates) 512 10/15 226 2 765 器件b(10 M Gates) 512 32/15 226 2 787 器件c(30 M Gates) 512 99/15 226 2 854 器件d(50 M Gates) 512 158/15 226 2 913 器件e(70 M Gates) 512 210/15 226 2 965 器件f(90 M Gates) 512 268/15 226 2 1023 *注:器件模型均屬一個系列,該系列包含10種復用單元 下載: 導出CSV
表 2 不同電路設計、相同芯片規(guī)模(同系列)下的碼流配置時間
電路設計 需要配置的
碼位總數(shù)(bit)碼流配置
時間(s)電路1(用滿25 k Gates器件資源) 5.8 k 0.016 電路2(用滿1 M Gates器件資源) 250.4 k 0.682 電路3(用滿10 M Gates器件資源) 2.3 M 6.360 電路4(用滿30 M Gates器件資源) 7.0 M 19.419 電路5(用滿50 M Gates器件資源) 11.5 M 30.334 電路6(用滿80 M Gates器件資源) 18.4 M 50.886 下載: 導出CSV
表 3 相同電路設計、不同芯片規(guī)模(同系列)下的碼流配置時間
器件模型 映射層數(shù)l 全器件的碼位總數(shù)n(bit) 平面化映射碼流(傳統(tǒng)方法)
配置時間t1(s)層次化映射碼流(本文方法)
配置時間t2(s)器件1(25.8 k Gates) 3 12.5 k 1.4 0.013 器件2(130 k Gates) 4 62.5 k 7.0 0.013 器件3(645 k Gates) 5 312.5 k 34.1 0.014 器件4(3.1 M Gates) 6 1.5 M 155.2 0.015 器件5(16.1 M Gates) 7 7.8 M 820.2 0.015 器件6(80.6 M Gates) 8 39 M 4066.0 0.016 下載: 導出CSV
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