基于FPGA的卷積神經(jīng)網(wǎng)絡(luò)硬件加速器設(shè)計
doi: 10.11999/JEIT190058
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華南理工大學(xué)電子與信息學(xué)院 ??廣州 ??510641
基金項目: 廣東省科技計劃項目(2014B090910002)
Design of Convolutional Neural Networks Hardware Acceleration Based on FPGA
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School of Electronics and Information Engineering, South China University of Technology, Guangzhou 510641, China
Funds: The Science and Technology Project of Guangdong Provience (2014B090910002)
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摘要: 針對卷積神經(jīng)網(wǎng)絡(luò)(CNN)計算量大、計算時間長的問題，該文提出一種基于現(xiàn)場可編程邏輯門陣列(FPGA)的卷積神經(jīng)網(wǎng)絡(luò)硬件加速器。首先通過深入分析卷積層的前向運算原理和探索卷積層運算的并行性，設(shè)計了一種輸入通道并行、輸出通道并行以及卷積窗口深度流水的硬件架構(gòu)。然后在上述架構(gòu)中設(shè)計了全并行乘法-加法樹模塊來加速卷積運算和高效的窗口緩存模塊來實現(xiàn)卷積窗口的流水線操作。最后實驗結(jié)果表明，該文提出的加速器能效比達(dá)到32.73 GOPS/W，比現(xiàn)有的解決方案高了34%，同時性能達(dá)到了317.86 GOPS。
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關(guān)鍵詞:
- 卷積神經(jīng)網(wǎng)絡(luò) /
- 硬件加速 /
- 現(xiàn)場可編程邏輯門陣列 /
- 計算并行 /
- 深度流水
Abstract: Considering the large computational complexity and the long-time calculation of Convolutional Neural Networks (CNN), an Field-Programmable Gate Array(FPGA)-based CNN hardware accelerator is proposed. Firstly, by deeply analyzing the forward computing principle and exploring the parallelism of convolutional layer, a hardware architecture in which parallel for the input channel and output channel, deep pipeline for the convolution window is presented. Then, a full parallel multi-addition tree is designed to accelerate convolution and efficient window buffer to implement deep pipelining operation of convolution window. The experimental results show that the energy efficiency ratio of proposed accelerator reaches 32.73 GOPS/W, which is 34% higher than the existing solutions, as the performance reaches 317.86 GOPS. -
表 1 卷積神經(jīng)網(wǎng)絡(luò)結(jié)構(gòu)參數(shù)
層名稱 層結(jié)構(gòu) 參數(shù)量（個） 卷積層1 卷積核大小3×3，卷積核個數(shù)15，步長1 150 激活層1 無 0 池化層1 池化大小2×2，步長2 0 卷積層2 卷積核大小6×6，卷積核個數(shù)20，步長1 10820 激活層2 無 0 池化層2 池化大小2×2，步長2 0 全連接層 輸出神經(jīng)元個數(shù)10 3210 
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表 3 與文獻(xiàn)FPGA硬件加速對比
文獻(xiàn)[7] 文獻(xiàn)[11] 文獻(xiàn)[12] 本文方法 FPGA Zynq XC7Z045 ZynqXC7Z045 Virtex-7 VX690T Cyclone V 5CGXF 頻率(MHz) 150 100 150 100 DSP資源 780(86.7%) 824(91.6%) 1376(38%) 342(100%) 量化策略 16 bit fixed 16 bit fixed 16 bit fixed 16 bit fixed 功耗(W) 9.630 9.400 25.000 9.711 性能(GOPS) 136.97 229.50 570.00 317.86 能效比(GOPS/W) 14.22 24.42 22.80 32.73
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