低熱梯度導向的三維FPGA互連通道網(wǎng)絡架構研究
doi: 10.11999/JEIT181134
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1.
中國科學院電子學研究所 北京 100190
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2.
中國科學院大學 北京 100049
基金項目: 國家自然科學基金(61876172, 61704173)，北京市科技重大專項課題(Z171100000117019)
Research into Low Thermal Gradient Oriented 3D FPGA Interconnect Channel Architecture Design
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1.
Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
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2.
University of Chinese Academy of Sciences, Beijing 100049, China
Funds: The National Natural Science Foundation of China (61876172, 61704173), The Major Program of Beijing Science and Technology (Z171100000117019)
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摘要: 該文針對3維FPGA (3D FPGA)芯片存在的散熱問題，提出具有低熱梯度特征的互連網(wǎng)絡通道結構，力圖解決傳統(tǒng)FPGA勻稱互連通道設計在芯片堆疊實現(xiàn)上產(chǎn)生的溫度非平衡現(xiàn)象。該文建立了3D FPGA的熱阻網(wǎng)絡模型；對不同類型的通道線對3D FPGA的熱分布影響進行了理論分析和熱仿真；提出了垂直方向通道網(wǎng)絡非均勻分布的3D FPGA通道結構，實驗表明，與給定傳統(tǒng)FPGA互連通道結構相比，采用所提方法實現(xiàn)的3D FPGA設計架構能夠降低76.8%的層間最高溫度梯度，10.4%的層內溫度梯度。
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關鍵詞:
- 3維現(xiàn)場可編程門陣列 /
- 非均勻通道結構 /
- 熱分布
Abstract: To solve the problem of heat dissipation in Three Dimensional Field Programmable Gate Array Technology (3D FPGA), an interconnect channel architectural design method with low thermal gradient feature is proposed. A thermal resistance network model is established for the 3D FPGA, and theoretical studies and thermal simulation experiments are carried out on the influence of different types of channels on the thermal performance of 3D FPGA. Further, non-uniform vertical direction channel structures of 3D FPGA are proposed. Experiments indicate that 3D FPGA designed using the method proposed can reduce the maximum temperature gradient between different layers by 76.8% and the temperature gradient within the same layer by 10.4% compared with the traditional channel structure of 3D FPGA. -
表 2 封裝材料設置
部件 材料 尺寸 切片 Si 8 mm×6 mm TSV Cu 直徑：20 μm，高度：50 μm Micro-Bump (微凸塊) Cu 高度：20 μm Ceramic substrate (陶瓷襯底) 氧化鋁 30 mm×30 mm BGA solder ball (BGA焊球) Sn63/Pb37 直徑：0.6 mm，中心距：1 mm PCB motherboard (PCB板) FR4 30 mm×30 mm 
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表 3 新結構熱分析統(tǒng)計結果
最低溫度(°C) 最高溫度(°C) 平均溫度(°C) 切片1 40.9203 45.1598 43.6753 切片2 41.7091 45.2051 43.9975 切片3 42.1229 45.2337 44.1000 切片4 42.3739 45.2715 44.2322
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表 4 層間熱梯度改善情況
最低溫度梯度
(°C)最高溫度梯度
(°C)平均溫度梯度
(°C)傳統(tǒng)結構 1.4601 0.4824 0.6717 新結構 1.4536 0.1117 0.5569 改善比例(%) 0.4 76.8 17.1
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表 5 層內熱梯度改善情況
切片1 切片2 切片3 切片4 傳統(tǒng)結構溫度差(°C) 4.2112 3.6969 3.3647 3.2335 新結構溫度差(°C) 4.2395 3.4960 3.1108 2.8976 改善比例(%) –0.60 5.40 7.50 10.40
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TRIMBERGER S M. Three ages of FPGAs: A retrospective on the first thirty years of FPGA technology[J]. Proceedings of the IEEE, 2015, 103(3): 318–331. doi: 10.1109/JPROC.2015.2392104 YANG Haigang. Overview: Emerging technologies on giga-scale FPGA implementat[C]. 2010 IEEE International Symposium on Circuits and Systems, Paris, France, 2010: 1428–1431. ZHANG Zhiping, LIAUW Y Y, CHEN Chen, et al. Monolithic 3-D FPGAs[J]. Proceedings of the IEEE, 2015, 103(7): 1197–1210. doi: 10.1109/JPROC.2015.2433954 ABABEI C, MOGAL H, and BAZARGAN K. Three-dimensional place and route for FPGAs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(6): 1132–1140. doi: 10.1109/TCAD.2005.855945 SIOZIOS K, SOTIRIADIS K, PAVLIDIS V F, et al. A software-supported methodology for designing high-performance 3D FPGA architectures[C]. 2007 IFIP International Conference on Very Large Scale Integration, Atlanta, GA, USA, 2007: 54–59. XILINX Corporation. Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency[EB/OL]. http://www.xilinx.com/technology/roadmap/ssi-technology, 2012: 1–10. Intel Corporation. Intel stratix 10 GX/SX device overview[EB/OL]. http://www.intel.com/content/www/us/en/programmable/documentation/joc1442261161666.html, 2018: 3–37. SALAH K. Survey on 3D-ICs thermal modeling, analysis, and management techniques[C]. The 19th IEEE Electronics Packaging Technology Conference, Singapore, 2017: 1–4. ZHAO Yi, HAO Cong, and YOSHIMURA T. TSV assignment of thermal and wirelength optimization for 3D-IC routing[C]. The 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, Platja d’Aro, Spain, 2018: 155–162. CONG J and ZHANG Yan. Thermal via planning for 3-D ICs[C]. 2005 IEEE/ACM International Conference on Computer-Aided Design, San Jose, USA, 2005: 745–752. GOPLEN B and SAPATNEKAR S S. Placement of thermal vias in 3-D ICs using various thermal objectives[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(4): 692–709. doi: 10.1109/TCAD.2006.870069 HSU P Y, CHEN H T, and HWANG T T. Stacking signal TSV for thermal dissipation in global routing for 3-D IC[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014, 33(7): 1031–1042. doi: 10.1109/TCAD.2014.2307488 ABABEI C, MOGAL H, and BAZARGAN K. Three-dimensional place and route for FPGAs[C]. 2005 Asia and South Pacific Design Automation Conference, Shanghai, China, 2005: 773–778. PANGRACIOUS V, MEHREZ H, and MARAKCHI Z. TSV count minimization and thermal analysis for 3D tree-based FPGA[C]. 2013 International Conference on IC Design & Technology, Pavia, Italy, 2013: 223–226. PAVLIDIS V F and FRIEDMAN E G, 著. 三維集成電路設計[M]. 繆旻, 于民, 金玉豐, 譯. 北京: 機械工業(yè)出版社, 2013: 1–209.PAVLIDIS V F and FRIEDMAN E G. Three-Dimensional Integrated Circuit Design[M]. MU Min, YU Min, JIN Yufeng, Translation. Beijing: Machinery Industry Press, 2013: 1–209. -
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