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一種快速響應無片外電容低壓差線性穩(wěn)壓器

佟星元 李茂 董嗣萬

佟星元, 李茂, 董嗣萬. 一種快速響應無片外電容低壓差線性穩(wěn)壓器[J]. 電子與信息學報, 2019, 41(11): 2592-2598. doi: 10.11999/JEIT181060
引用本文: 佟星元, 李茂, 董嗣萬. 一種快速響應無片外電容低壓差線性穩(wěn)壓器[J]. 電子與信息學報, 2019, 41(11): 2592-2598. doi: 10.11999/JEIT181060
Xingyuan TONG, Mao LI, Siwan DONG. A Capacitor-less Low Dropout Regulator with Fast Response[J]. Journal of Electronics & Information Technology, 2019, 41(11): 2592-2598. doi: 10.11999/JEIT181060
Citation: Xingyuan TONG, Mao LI, Siwan DONG. A Capacitor-less Low Dropout Regulator with Fast Response[J]. Journal of Electronics & Information Technology, 2019, 41(11): 2592-2598. doi: 10.11999/JEIT181060

一種快速響應無片外電容低壓差線性穩(wěn)壓器

doi: 10.11999/JEIT181060
基金項目: 國家自然科學基金(61674122,61804124),陜西省創(chuàng)新人才推進計劃(2017KJXX-46),陜西省高層次人才特殊支持計劃(2018-36)
詳細信息
    作者簡介:

    佟星元:男,1984年生,博士后,教授,研究方向為生物醫(yī)療電子、超低功耗模擬. 混合信號集成電路設計

    李茂:男,1994年生,碩士生,研究方向為電源管理及無線能量傳輸電路設計

    董嗣萬:男,1988年生,博士,講師,研究方向為模擬集成電路設計

    通訊作者:

    佟星元 mayxt@126.com

  • 中圖分類號: TN431.2

A Capacitor-less Low Dropout Regulator with Fast Response

Funds: The National Natural Science Foundation of China (61674122, 61804124), Shaanxi Innovation Talents Promotion Plan(2017KJXX-46), Shaanxi Provincial High-level Talents Special Support Plan (2018-36)
  • 摘要: 為了改善負載跳變對低壓差線性穩(wěn)壓器(LDO)的影響,該文提出一種用于無片外電容LDO(CL-LDO)的新型快速響應技術。通過增加一條額外的快速通路,實現(xiàn)CL-LDO的快速瞬態(tài)響應,并且能夠減小LDO輸出過沖和下沖的幅度。該文電路基于0.18 μm CMOS工藝設計實現(xiàn),面積為0.00529 mm2。流片測試結果表明,當輸入電壓范圍為1.5~2.5 V時,輸出電壓為1.194 V;當負載電流以 1 μs的上升時間和下降時間在 100 μA~10 mA之間變化時,CL-LDO的過沖恢復時間為489.537 ns,下沖恢復為960.918 ns;相比未采用該技術的傳統(tǒng)CL-LDO,響應速度能夠提高7.41倍,輸出過沖和下沖的電壓幅值能夠分別下降35.3%和78.1%。
  • 圖  1  傳統(tǒng)LDO和CL-LDO結構

    圖  2  本文提出CL-LDO的整體結構

    圖  3  本文提出CL-LDO的工作原理

    圖  4  本文提出的快速瞬態(tài)調(diào)節(jié)電路

    圖  5  本文CL-LDO的小信號模型等效電路

    圖  6  環(huán)路特性仿真結果

    圖  7  本文提出CL-LDO的芯片照片和版圖

    圖  8  本文CL-LDO的瞬態(tài)測試結果

    圖  9  本文CL-LDO的直流特性測試結果

    表  1  控制信號Ctrl1和Ctrl2的工作原理

    ILVfbCtrl1Ctrl2M1M2
    升高下沖/<0.70 V低電平低電平導通關斷
    降低過沖/>0.90 V高電平高電平關斷導通
    穩(wěn)定穩(wěn)定/=0.80 V高電平低電平關斷關斷
    下載: 導出CSV

    表  2  本文設計的CL-LDO與其它文獻的CL-LDO性能比較

    參數(shù)文獻[13]*文獻[14]文獻[15]文獻[16]本文
    W/OW
    工藝 (nm)18065180130180
    Vin (V)1.21.21.2~1.81~1.41.5~2.5
    Vout (V)110.8~1.60.81.2
    IL (mA)1000.1~251-1000.12~250.1~10
    過沖/下沖 (mV)220225200284597/946386/207
    環(huán)路增益 (dB)>59.87585~8785~87
    負載調(diào)整率 (mV/mA)0.0230.0420.0810.1730.970.96
    線性調(diào)整率 (mV/V)0.693.82.2511.310.0
    恢復時間 (μs)3.61.3?0.22?0.19#3.6240.489
    電源抑制比 (dB)49.6525750.2
    面積 (mm2)0.0220.0870.0310.0080.00529
    *考慮寄生參數(shù)的電路后仿真數(shù)據(jù);電流階躍變化的上升時間和下降時間為1 μs;?電流階躍變化的上升時間和下降時間約為300 ps;#電流階躍變化的上升時間和下降時間約為100 ns。
    下載: 導出CSV
  • MILLIKEN R J, SILVA-MARTINEZ J, and SANCHEZ-SINENCIO E. Full on-chip CMOS low-dropout voltage regulator[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2007, 54(9): 1879–1890. doi: 10.1109/TCSI.2007.902615
    YEO J, JAVED K, LEE J, et al. A capacitorless low-dropout regulator with enhanced slew rate and 4.5-μA quiescent current[J]. Analog Integrated Circuits and Signal Processing, 2017, 90(1): 227–235. doi: 10.1007/s10470-016-0869-z
    TONG Xingyuan and SUN Tiantian. A programmable multi-output technique in LDO regulator for multi-reference SAR ADC application[J]. International Journal of Electronics, 2017, 104(3): 528–538. doi: 10.1080/00207217.2016.1218069
    HUANG W J, LU S H, and LIU Shenluan. A capacitor-free CMOS low dropout regulator with slew rate enhancement[C]. Proceedings of 2006 International Symposium on VLSI Design, Automation and Test, Hsinchu, China, 2006: 1–4.
    LIU Nanqi, JOHNSON B, NADIG V, et al. A transient-enhanced fully-integrated LDO regulator for SoC application[C]. Proceedings of 2018 IEEE International Symposium on Circuits and Systems, Florence, Italy, 2018: 1–5.
    LEUNG K N and NG Y S. A CMOS low-dropout regulator with a momentarily current-boosting voltage buffer[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2010, 57(9): 2312–2319. doi: 10.1109/TCSI.2010.2043171
    AL-SHYOUKH M, LEE H, and PEREZ R. A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenuation[J]. IEEE Journal of Solid-State Circuits, 2007, 42(8): 1732–1742. doi: 10.1109/JSSC.2007.900281
    TONG Xingyuan and WEI Kangkang. A fully integrated fast-response LDO voltage regulator with adaptive transient current distribution[C]. Proceedings of 2017 IEEE Computer Society Annual Symposium on VLSI, Bochum, Germany, 2017: 651–654.
    MARANO D, GRASSO A D, PALUMBO G, et al. Optimized active single-miller capacitor compensation with inner half-feedforward stage for very high-load three-stage OTAs[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2016, 63(9): 1349–1359. doi: 10.1109/TCSI.2016.2573920
    ZENG Yanhan, LI Yuao, ZHANG Xin, et al. A push-pulled FVF based output-capacitorless LDO with adaptive power transistors[J]. Microelectronics Journal, 2017, 64: 69–77. doi: 10.1016/j.mejo.2017.04.008
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    SHIRMOHAMMADLI V, SABERKARI A, MARTINEZ-GARCIA H, et al. Low power output-capacitorless class-AB CMOS LDO regulator[C]. Proceedings of 2017 IEEE International Symposium on Circuits and Systems, Baltimore, USA, 2017: 1–4.
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出版歷程
  • 收稿日期:  2018-11-20
  • 修回日期:  2019-03-07
  • 網(wǎng)絡出版日期:  2019-04-10
  • 刊出日期:  2019-11-01

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