一種快速響應無片外電容低壓差線性穩(wěn)壓器
doi: 10.11999/JEIT181060
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西安郵電大學電子工程學院 西安 710121
基金項目: 國家自然科學基金(61674122,61804124),陜西省創(chuàng)新人才推進計劃(2017KJXX-46),陜西省高層次人才特殊支持計劃(2018-36)
A Capacitor-less Low Dropout Regulator with Fast Response
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School of Electronics Engineering, Xi’an University of Posts and Telecommunications, Xi’an 710121, China
Funds: The National Natural Science Foundation of China (61674122, 61804124), Shaanxi Innovation Talents Promotion Plan(2017KJXX-46), Shaanxi Provincial High-level Talents Special Support Plan (2018-36)
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摘要: 為了改善負載跳變對低壓差線性穩(wěn)壓器(LDO)的影響,該文提出一種用于無片外電容LDO(CL-LDO)的新型快速響應技術。通過增加一條額外的快速通路,實現(xiàn)CL-LDO的快速瞬態(tài)響應,并且能夠減小LDO輸出過沖和下沖的幅度。該文電路基于0.18 μm CMOS工藝設計實現(xiàn),面積為0.00529 mm2。流片測試結果表明,當輸入電壓范圍為1.5~2.5 V時,輸出電壓為1.194 V;當負載電流以 1 μs的上升時間和下降時間在 100 μA~10 mA之間變化時,CL-LDO的過沖恢復時間為489.537 ns,下沖恢復為960.918 ns;相比未采用該技術的傳統(tǒng)CL-LDO,響應速度能夠提高7.41倍,輸出過沖和下沖的電壓幅值能夠分別下降35.3%和78.1%。
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關鍵詞:
- 低壓差穩(wěn)壓器 /
- 無片外電容 /
- 快速瞬態(tài)響應 /
- 面積小
Abstract: A novel technique for increasing the load response speed of Capacitor-Less Low-DropOut linear regulator (CL-LDO) is proposed to improve the transient response of CL-LDO when its load current changes. With an additional fast signal feedback path, the CL-LDO can achieve fast transient response so that the overshoot and undershoot of its output voltage can be dramatically reduced. A CL-LDO with fast response is realized in 0.18 μm CMOS and occupies an active area of 0.00529 mm2. The CL-LDO has an output voltage of 1.194 V when the input supply voltage ranges from 1.5 V to 2.5 V. When the load current changes from 100 μA to 10 mA with the rise and fall time of 1 μs, the output of LDO can be recovered from its overshoot and undershoot to a stable voltage within 489.537 ns and 960.918 ns, respectively. Compared with a traditional CL-LDO without this proposed technique, the transient response speed of this CL-LDO is increased by 7.41 times. The overshoot and undershoot of the output voltage is decreased by 35.3% and 78.1%, respectively.-
Key words:
- Low-DropOut (LDO) regulator /
- Capacitor-less /
- Fast transient response /
- Small area
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表 1 控制信號Ctrl1和Ctrl2的工作原理
IL Vfb Ctrl1 Ctrl2 M1 M2 升高 下沖/<0.70 V 低電平 低電平 導通 關斷 降低 過沖/>0.90 V 高電平 高電平 關斷 導通 穩(wěn)定 穩(wěn)定/=0.80 V 高電平 低電平 關斷 關斷 下載: 導出CSV
表 2 本文設計的CL-LDO與其它文獻的CL-LDO性能比較
參數(shù) 文獻[13]* 文獻[14] 文獻[15] 文獻[16] 本文 W/O W 工藝 (nm) 180 65 180 130 180 Vin (V) 1.2 1.2 1.2~1.8 1~1.4 1.5~2.5 Vout (V) 1 1 0.8~1.6 0.8 1.2 IL (mA) 100 0.1~25 1-100 0.12~25 0.1~10 過沖/下沖 (mV) 220 225 200 284 597/946 386/207 環(huán)路增益 (dB) – – >59.8 75 85~87 85~87 負載調(diào)整率 (mV/mA) 0.023 0.042 0.081 0.173 0.97 0.96 線性調(diào)整率 (mV/V) 0.69 3.8 – 2.25 11.3 10.0 恢復時間 (μs) 3.6* 1.3? 0.22? 0.19# 3.624* 0.489* 電源抑制比 (dB) 49.6 52 – 57 50.2 面積 (mm2) 0.022 0.087 0.031 0.008 0.00529 *考慮寄生參數(shù)的電路后仿真數(shù)據(jù);*電流階躍變化的上升時間和下降時間為1 μs;?電流階躍變化的上升時間和下降時間約為300 ps;#電流階躍變化的上升時間和下降時間約為100 ns。 下載: 導出CSV
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