一種低延遲的3維高效視頻編碼中深度建模模式編碼器

王莉; 曹一凡; 杜高明; 劉冠宇; 王曉蕾; 張多利

doi:10.11999/JEIT180798

一種低延遲的3維高效視頻編碼中深度建模模式編碼器

doi: 10.11999/JEIT180798

合肥工業(yè)大學(xué)電子科學(xué)與應(yīng)用物理學(xué)院?合肥?230009

基金項(xiàng)目: 國(guó)家自然科學(xué)基金(61474036)，教育部IC設(shè)計(jì)網(wǎng)上合作研究中心項(xiàng)目(JSGG20170413153845042)

詳細(xì)信息

作者簡(jiǎn)介:
王莉：女，1977年生，副教授，博士，研究方向?yàn)榧{米材料和半導(dǎo)體器件

曹一凡：男，1994年生，碩士生，研究方向?yàn)橐曨l編解碼的數(shù)字集成電路設(shè)計(jì)

杜高明：男，1977年生，副研究員，博士，研究方向?yàn)槎嗪思呻娐敷w系結(jié)構(gòu)、2維/3維片上網(wǎng)絡(luò)集成體系結(jié)構(gòu)

劉冠宇：男，1995年生，碩士生，研究方向?yàn)閿?shù)字集成電路設(shè)計(jì)

王曉蕾：女，1978年生，副研究員，碩士，研究方向?yàn)榧呻娐吩O(shè)計(jì)

張多利：男，1976年生，研究員，博士，研究方向?yàn)槎嗪颂幚砥黧w系架構(gòu)和設(shè)計(jì)方法

通訊作者:
杜高明　dugaoming@hfut.edu.cn

中圖分類號(hào): TN47; TN919.81
計(jì)量
- 文章訪問(wèn)數(shù): 1616
- HTML全文瀏覽量: 756
- PDF下載量: 59
- 被引次數(shù): 0
出版歷程
- 收稿日期: 2018-08-16
- 修回日期: 2019-02-27
- 網(wǎng)絡(luò)出版日期: 2019-03-18
- 刊出日期: 2019-07-01

A Low-latency Depth Modelling Mode-1 Encoder in 3D-high Efficiency Video Coding Standard

School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei 230009, China

Funds: The National Natural Science Foundation of China(61474036), The Project of IC Design Web-cooperation Research Center of MOE(JSGG20170413153845042)

摘要

摘要: 為了更好地對(duì)3D視頻中深度圖進(jìn)行編碼，該文將3維高效視頻編碼(3D-HEVC)標(biāo)準(zhǔn)新引入了深度建模模式(DMMs)，新模式在提高了編碼質(zhì)量的同時(shí)改進(jìn)了原有算法的復(fù)雜度。在設(shè)計(jì)DMM-1編碼器電路時(shí)，傳統(tǒng)架構(gòu)電路的編碼周期均較長(zhǎng)，只能滿足較低分辨率和幀率的視頻實(shí)時(shí)編碼要求。為了進(jìn)一步提高3D-HEVC中DMM-1編碼器的性能，該文對(duì)DMM-1算法架構(gòu)進(jìn)行了研究，針對(duì)其中楔形塊評(píng)估無(wú)數(shù)據(jù)相關(guān)性的特點(diǎn)，提出了一種5級(jí)流水線架構(gòu)的DMM-1編碼器硬件電路，以期能夠降低一個(gè)深度塊編碼所需的編碼周期，并使用Verilog HDL進(jìn)行實(shí)現(xiàn)。實(shí)驗(yàn)表明：該架構(gòu)與Sanchez等人(2017年)的工作相比，以電路門數(shù)增加約1568門為代價(jià)，可減少至少52.3%的編碼周期。
- 3維高效視頻編碼 /
- 深度圖 /
- 幀內(nèi)預(yù)測(cè) /
- 深度建模模式算法 /
- Verilog
Abstract: In order to encode better the depth maps in 3D video, the 3D-High Efficiency Video Coding (3D-HEVC) standard is introduced in Depth Modeling Modes(DMMs), which increase the quality of original algorithm while improving the encoding complexity. The traditional architecture of DMM-1 encoder circuit has a longer coding period and can only meet real-time coding requirements of lower resolution and frame rate. In order to improve the performance of DMM-1 encoder, the structure of DMM-1 algorithm is researched and a five-stage pipeline architecture of DMM-1 encoder is proposed. The pipeline architecture can reduce the coding cycles. The architecture is implemented by Verilog HDL. Experiments show that this architecture can reduce the coding cycle by at least 52.3%, at the cost of 1568 gates compared to previous work by Sanchez G. et al. (2017).
- 3D-High Efficiency Video Coding (3D-HEVC) /
- Depth map /
- Intra prediction /
- Depth Modelling Mode (DMM) algorithm /
- Verilog

HTML全文

圖 1 3D-HEVC編解碼流程圖

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圖 2 紋理圖和深度圖示意圖

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圖 3 深度圖幀內(nèi)預(yù)測(cè)流程圖

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圖 4 DMM-1和DMM-4示意圖

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圖 5 DMM-1算法流程圖

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圖 6 DMM-1算法計(jì)算實(shí)例圖

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圖 7 流水線架構(gòu)電路時(shí)序圖

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圖 8 楔形塊數(shù)據(jù)庫(kù)存儲(chǔ)模塊結(jié)構(gòu)圖

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圖 9 搜索模塊結(jié)構(gòu)圖

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圖 10 4組測(cè)試激勵(lì)及預(yù)測(cè)結(jié)果示意圖

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圖 11 楔形塊編碼周期對(duì)比示意圖

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圖 12 楔形塊編碼時(shí)間對(duì)比示意圖

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表 1 深度圖幀內(nèi)預(yù)測(cè)模式序號(hào)和名稱

模式序號(hào)	模式名稱
0	Planar
1	DC
2～34	Directional
35	DMM-1
36	DMM-4

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表 2 流水線架構(gòu)性能和對(duì)比

工作	塊尺寸	工藝(nm)	門數(shù)	頻率(MHz)	周期/塊	時(shí)間/塊(ns)
本文	4×4	Nangate 45	4859	350.0	63	179.5
文獻(xiàn)[15]	4×4	ST 65	4070	515.5	134	259.9
文獻(xiàn)[16]	4×4	ST 65	3291	514.3	132	256.7

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參考文獻(xiàn)(16)

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SHEN Liquan, ZHANG Zhaoyang, and LIU Zhi. Inter mode selection for depth map coding in 3D video[J]. IEEE Transactions on Consumer Electronics, 2012, 58(3): 926–931. doi: 10.1109/TCE.2012.6311338

CERNIGLIARO G, JAUREGUIZAR F, CABRERA J, et al. Low complexity mode decision and motion estimation for H.264/AVC based depth maps encoding in free viewpoint video[J]. IEEE Transactions on Circuits and Systems for Video Technology, 2013, 23(5): 769–783. doi: 10.1109/TCSVT.2012.2223632

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GUO Ruixue, HE Gang, LI Yunsong, et al. Fast algorithm for prediction unit and mode decisions of intra depth coding in 3D-HEVC[C]. Proceedings of 2016 IEEE International Conference on Image Processing, Phoenix, Arizona, USA, 2016: 1121–1125.

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粘春湄, 陳婧, 曾煥強(qiáng). 紋理類型預(yù)判和SDC優(yōu)化的3D-HEVC深度圖幀內(nèi)算法[J]. 計(jì)算機(jī)科學(xué)與探索, 2018, 12(6): 994–1003. doi: 10.3778/j.issn.1673-9418.1711040

NIAN Chunmei, CHEN Jing, and ZENG Huanqiang. Depth map intra algorithm for 3D-HEVC by prejudging texture type and SDC optimization[J]. Journal of Frontiers of Computer Science and Technology, 2018, 12(6): 994–1003. doi: 10.3778/j.issn.1673-9418.1711040

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