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FPGA硬核處理器系統(tǒng)加速數(shù)字電路功能驗(yàn)證的方法

劉小強(qiáng) 袁國順 喬樹山

劉小強(qiáng), 袁國順, 喬樹山. FPGA硬核處理器系統(tǒng)加速數(shù)字電路功能驗(yàn)證的方法[J]. 電子與信息學(xué)報(bào), 2019, 41(5): 1251-1256. doi: 10.11999/JEIT180641
引用本文: 劉小強(qiáng), 袁國順, 喬樹山. FPGA硬核處理器系統(tǒng)加速數(shù)字電路功能驗(yàn)證的方法[J]. 電子與信息學(xué)報(bào), 2019, 41(5): 1251-1256. doi: 10.11999/JEIT180641
Xiaoqiang LIU, Guoshun YUAN, Shushan QIAO. Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System[J]. Journal of Electronics & Information Technology, 2019, 41(5): 1251-1256. doi: 10.11999/JEIT180641
Citation: Xiaoqiang LIU, Guoshun YUAN, Shushan QIAO. Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System[J]. Journal of Electronics & Information Technology, 2019, 41(5): 1251-1256. doi: 10.11999/JEIT180641

FPGA硬核處理器系統(tǒng)加速數(shù)字電路功能驗(yàn)證的方法

doi: 10.11999/JEIT180641
基金項(xiàng)目: 國家自然科學(xué)基金(61474135)
詳細(xì)信息
    作者簡介:

    劉小強(qiáng):男,1990年生,博士生,研究方向?yàn)镾oC芯片設(shè)計(jì)、圖像識別

    袁國順:男,1966年生,博士生導(dǎo)師、研究員,研究方向?yàn)榍度胧組CU設(shè)計(jì)、高性能模數(shù)混合電路

    喬樹山:男,1980年生,碩士生導(dǎo)師、研究員,研究方向?yàn)榈凸募呻娐吩O(shè)計(jì)方法學(xué)、智能感知節(jié)點(diǎn)SoC、無線通信、電力線載波通信、數(shù)字化射頻接收機(jī)、低功耗處理器

    通訊作者:

    袁國順 mryuangs@hotmail.com

  • 中圖分類號: TN492

Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System

Funds: The National Natural Science Foundation of China (61474135)
  • 摘要: 為了縮短專用集成電路和片上系統(tǒng)的功能驗(yàn)證周期,該文提出FPGA硬核處理器系統(tǒng)加速數(shù)字電路功能驗(yàn)證的方法。所提方法綜合軟件仿真功能驗(yàn)證和現(xiàn)場可編程門陣列原型驗(yàn)證的優(yōu)點(diǎn),利用集成在片上系統(tǒng)現(xiàn)場可編程門陣列器件中的硬核處理器系統(tǒng)作為驗(yàn)證激勵發(fā)生單元和功能驗(yàn)證覆蓋率分析單元,解決了驗(yàn)證速度和靈活性不能統(tǒng)一的問題。與軟件仿真驗(yàn)證相比,所提方法可以有效縮短數(shù)字電路的功能驗(yàn)證時間;在功能驗(yàn)證效率和驗(yàn)證知識產(chǎn)權(quán)可重用方面表現(xiàn)優(yōu)于現(xiàn)有的FPGA原型驗(yàn)證技術(shù)。
  • 圖  1  軟件仿真驗(yàn)證平臺

    圖  2  驗(yàn)證系統(tǒng)硬件實(shí)現(xiàn)圖

    圖  4  驗(yàn)證軟硬件分割圖

    圖  3  功能驗(yàn)證技術(shù)的實(shí)現(xiàn)流程圖

    圖  5  不同驗(yàn)證技術(shù)對比結(jié)果

    表  1  本文提出的技術(shù)與其他文獻(xiàn)的結(jié)果對比

    采用技術(shù) 功能覆蓋率(%) 高級語言 驗(yàn)證時長(s) 通信帶寬(Gb/s) 驗(yàn)證IP復(fù)用 頻率(MHz)
    軟件仿真驗(yàn)證[4,5] 100 203572
    傳統(tǒng)FPGA原型驗(yàn)證[7,8] 594 63.5
    改進(jìn)FPGA原型驗(yàn)證[9,10] 100 357 1.00 58.3
    本文所提出的技術(shù) 100 179 25.20 98.6
    下載: 導(dǎo)出CSV
  • WANG Yifan, JOERES S, WUNDERLICH R, et al. Modeling approaches for functional verification of RF-SoCs: Limits and future requirements[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009, 28(5): 769–773. doi: 10.1109/TCAD.2009.2014533
    MARKOVIC D, CHANG Chen, RICHARDS R, et al. ASIC design and verification in an FPGA environment[C]. Proceedings of 2007 IEEE Custom Integrated Circuits Conference, San Jose, USA, 2007: 737–740.
    STOTLAND I, SHPAGILEV D, and STARIKOVSKAYA N. UVM based approaches to functional verification of communication controllers of microprocessor systems[C]. Proceedings of 2016 IEEE East-West Design & Test Symposium, Yerevan, Armenia, 2016: 1–4.
    HU Zhaohui, PIERRES A, HU Shiqing, et al. Practical and efficient SOC verification flow by reusing IP testcase and testbench[C]. Proceedings of 2012 International SoC Design Conference, Jeju Island, South Korea, 2012: 175–178.
    KIM M, KONG J, SUH T, et al. Latch-based FPGA emulation method for design verification: Case study with microprocessor[J]. Electronics Letters, 2011, 47(9): 532–533. doi: 10.1049/el.2011.0462
    施佺, 韓賽飛, 黃新明, 等. 面向全同態(tài)加密的有限域FFT算法FPGA設(shè)計(jì)[J]. 電子與信息學(xué)報(bào), 2018, 40(1): 57–62. doi: 10.11999/JEIT170312

    SHI Quan, HAN Saifei, HUANG Xinming, et al. Design of finite field FFT for fully homomorphic encryption based on FPGA[J]. Journal of Electronics &Information Technology, 2018, 40(1): 57–62. doi: 10.11999/JEIT170312
    LI Tiejun, ZHANG Jianmin, and LI Sikun. An FPGA-based random functional verification method for cache[C]. Proceedings of the 2013 IEEE 8th International Conference on Networking, Architecture and Storage, Xi'an, China, 2013: 277–281.
    GSCHWIND M, SALAPURA V, and MAURER D. FPGA prototyping of a RISC processor core for embedded applications[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001, 9(2): 241–250. doi: 10.1109/92.924027
    PODIVINSKY J, CEKAN O, LOJDA J, et al. Functional verification based platform for evaluating fault tolerance properties[J]. Microprocessors and Microsystems, 2017, 52: 145–159. doi: 10.1016/j.micpro.2017.06.004
    BARNASCONI M, DIETRICH M, EINWICH K, et al. UVM-systemC-AMS framework for system-level verification and validation of automotive use cases[J]. IEEE Design & Test, 2015, 32(6): 76–86. doi: 10.1109/MDAT.2015.2427260
    IEEE. 1800.2-2017 IEEE standard for universal verification methodology language reference manual[S]. IEEE, 2017.
    CHEN Fulong and SUN Yunxiang. FPGA-based elastic in-circuit debugging for complex digital logic design[J]. International Journal of Autonomous and Adaptive Communications Systems, 2017, 10(3): 303–319. doi: 10.1504/IJAACS.2017.10007621
    Intel FPGA. Cyclone V hard processor system technical reference manual[EB/OL]. https://www.altera.com/documentation/sfo1410143707420.html, 2018: 6.
    Xilinx Inc. Zynq-7000 all programmable SoC data sheet: Overview[EB/OL]. https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#documentation, 2018: 6.
    DUARTE-SáNCHEZ J E, VELASCO-MEDINA J, and MORENO P A. Hardware accelerator for the multifractal analysis of DNA sequences[J]. IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2018, 15(5): 1611–1624. doi: 10.1109/TCBB.2017.2731339
    ISKANDER Y, PATTERSON C, and CRAVEN S. High-level abstractions and modular debugging for FPGA design validation[J]. ACM Transactions on Reconfigurable Technology and Systems, 2014, 7(1): 1–22. doi: 10.1145/2567662
    SCHAFER B C. Source code error detection in High-level synthesis functional verification[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(1): 301–312. doi: 10.1109/TVLSI.2015.2397036
  • 加載中
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計(jì)量
  • 文章訪問數(shù):  2039
  • HTML全文瀏覽量:  769
  • PDF下載量:  93
  • 被引次數(shù): 0
出版歷程
  • 收稿日期:  2018-07-02
  • 修回日期:  2018-01-10
  • 網(wǎng)絡(luò)出版日期:  2019-01-22
  • 刊出日期:  2019-05-01

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