FPGA硬核處理器系統(tǒng)加速數(shù)字電路功能驗(yàn)證的方法
doi: 10.11999/JEIT180641
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1.
中國科學(xué)院微電子研究所 ??北京 ??100029
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2.
中國科學(xué)院大學(xué) ??北京 ??100049
基金項(xiàng)目: 國家自然科學(xué)基金(61474135)
Accelerating Functional Verification for Digital Circuit with FPGA Hard Processor System
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1.
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
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2.
University of Chinese Academy of Sciences, Beijing 100049, China
Funds: The National Natural Science Foundation of China (61474135)
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摘要: 為了縮短專用集成電路和片上系統(tǒng)的功能驗(yàn)證周期，該文提出FPGA硬核處理器系統(tǒng)加速數(shù)字電路功能驗(yàn)證的方法。所提方法綜合軟件仿真功能驗(yàn)證和現(xiàn)場可編程門陣列原型驗(yàn)證的優(yōu)點(diǎn)，利用集成在片上系統(tǒng)現(xiàn)場可編程門陣列器件中的硬核處理器系統(tǒng)作為驗(yàn)證激勵發(fā)生單元和功能驗(yàn)證覆蓋率分析單元，解決了驗(yàn)證速度和靈活性不能統(tǒng)一的問題。與軟件仿真驗(yàn)證相比，所提方法可以有效縮短數(shù)字電路的功能驗(yàn)證時間；在功能驗(yàn)證效率和驗(yàn)證知識產(chǎn)權(quán)可重用方面表現(xiàn)優(yōu)于現(xiàn)有的FPGA原型驗(yàn)證技術(shù)。
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關(guān)鍵詞:
- 專用集成電路 /
- 功能驗(yàn)證 /
- 片上系統(tǒng) /
- FPGA原型驗(yàn)證 /
- SoC FPGA
Abstract: In order to reduce the functional verification cycle of application-specific integrated circuits and on-chip system, a method for accelerating functional verification with FPGA digital hard processor system is proposed. The proposed method combines the advantages of software simulation function verification and field programmable gate array prototype verification, and uses the hard processor system integrated in the on-chip system field programmable gate array device as the verification excitation generation and the function verification coverage analysis unit. It solves the problem that verification speed and flexibility can not be unified. Compared with software simulation verification, the proposed method can effectively shorten the functional verification time of digital circuits; it is superior to existing FPGA prototyping technology in terms of functional verification efficiency and verification of intellectual property reusability. -
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