高吞吐率雙模浮點可重構(gòu)FFT處理器設(shè)計實現(xiàn)
doi: 10.11999/JEIT180170
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1.
中國科學(xué)院電子學(xué)研究所 ??北京 ??100190
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2.
中國科學(xué)院大學(xué) ??北京 ??100190
基金項目: 國家自然科學(xué)基金(61704173, 61474120)，北京市科技重大專項課題(Z171100000117019)
High Throughput Dual-mode Reconfigurable Floating-point FFT Processor
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1.
Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China
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2.
University of Chinese Academy of Sciences, Beijing 100190, China
Funds: The National Natural Science Foundation of China (61704173, 61474120), The Major Program of Beijing Science and Technology (Z171100000117019)
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摘要: 高吞吐浮點可靈活重構(gòu)的快速傅里葉變換(FFT)處理器可滿足尖端雷達實時成像和高精度科學(xué)計算等多種應(yīng)用需求。與定點FFT相比，浮點運算復(fù)雜度更高，使得浮點型FFT的運算吞吐率與其實現(xiàn)面積、功耗之間的矛盾問題尤為突出。鑒于此，為降低運算復(fù)雜度，首先將大點數(shù)FFT分解成若干個小點數(shù)基2k 級聯(lián)子級實現(xiàn)，提出分別針對128/256/512/1024/2048點FFT的優(yōu)化混合基算法。同時，結(jié)合所提出同時支持單通道單精度和雙通道半精度兩種浮點模式的新型融合加減與點乘運算單元，首次提出一款高吞吐率雙模浮點可變點FFT處理器結(jié)構(gòu)，并在28 nm標準CMOS工藝下進行設(shè)計并實現(xiàn)。實驗結(jié)果表明，單通道單精度和雙通道半精度浮點兩種模式下的運算吞吐率和輸出平均信號量化噪聲比分別為3.478 GSample/s, 135 dB和6.957 GSample/s, 60 dB。歸一化吞吐率面積比相比于現(xiàn)有其他浮點FFT實現(xiàn)可提高約12倍。Abstract: In the advanced applications of real-time radar imaging and high-precision scientific computing systems, the design of high throughput and reconfigurable Floating-Point (FP) FFT accelerator is significant. Achieving high throughput FP FFT with low area and power cost poses a greater challenge due to high complexity of FP operations in comparison to fixed-point implementations. To address these issues, a serial of mixed-radix algorithms for 128/256/512/1024/2048-point FFT are proposed by decomposing long FFT into short implementations with cascaded radix-2k stages so that the complexity of multiplications can be significantly reduced. Besides, two novel fused FP add-subtract and dot-product units for dual-mode functionality are proposed, which can either compute on a pair of double precision operands or on two pairs of single precision operands in parallel. Thus, a high throughput dual-mode floating-point variable length FFT is designed. The proposed processor is implemented based on SMIC 28 nm CMOS technology. Simulation results show that the throughput and Signal-to-Quantization Noise Ratio (SQNR) in single-channel single precision and dual-channel half precision floating-point mode are 3.478 GSample/s, 135 dB and 6.957 GSample/s, 60 dB respectively. Compare to the other FP FFT, this processor can achieve 12 times improvement of normalized throughput-area ratio.
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表 1 本文所提出的混合基算法
點數(shù) 優(yōu)化算法 每個子級相應(yīng)的基底 1 2 3 4 5 6 7 8 9 10 128 23-22-22 4 8 128 4 16 4 256 24-22-22 4 16 4 256 4 16 4 512 24-22-23 4 16 4 512 4 32 4 8 1024 25-22-23 4 8 32 4 1024 4 32 4 8 2048 25-23-23 4 8 32 4 2048 4 8 64 4 8 
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表 2 雙模浮點融合加減運算單元關(guān)鍵路徑
模塊名 流水級 延時(ns) 數(shù)據(jù)提取與尾數(shù)生成 1 0.43 指數(shù)比較與尾數(shù)交換 1 0.77 指數(shù)階差與尾數(shù)對齊 2 1.98 尾數(shù)求和差 3 1.47 LZA 3 0.35 規(guī)格化左移 3 0.16
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表 3 雙模浮點融合加減運算單元性能比較結(jié)果
參數(shù) 文獻[6] 參考結(jié)構(gòu)T1 本文 工藝 (nm) 45 28 28 歸一化面積 (μm2) 5226 (100%) 2665 (51%) 2317 (44%) 工作頻率 (MHz) 1920 500 435 計算延遲 (ns) 1.0 6.0 6.9 功耗 (mW) 5.2 0.6 0.4 功耗×周期 2.70 (100%) 1.20 (44%) 0.84 (31%)
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表 4 雙模浮點融合點乘運算單元關(guān)鍵路徑
模塊名 流水級 延時(ns) 數(shù)據(jù)提取與指數(shù)比較 1 0.33 尾數(shù)部分積相乘 1 0.87 指數(shù)階差與乘積對齊 2 1.25 雙模4:2 CSA 2 0.20 雙加法舍入路徑 2 0.53 LZD與規(guī)格化左移 3 1.98
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表 5 雙模浮點融合點乘運算單元性能比較結(jié)果
參數(shù) 文獻[5] 參考結(jié)構(gòu)T2 本文 工藝 (nm) 45 28 28 歸一化面積 (μm2) 12865 (100%) 10336 (80%) 10701 (83%) 工作頻率 (MHz) 1493 500 435 計算延遲 (ns) 2.1 6.0 6.9 功耗 (mW) 16.9 2.7 2.5 功耗×周期 11.3 (100%) 5.3 (47%) 5.6 (50%)
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表 6 雙模浮點FFT整體性能對比
性能參數(shù) 文獻[2] 文獻[9] 文獻[16] 本文 工藝 (nm) 90 65 55 28 FFT結(jié)構(gòu) 基于存儲器 Hybrid MDF MDF FFT點數(shù) 512 1024 1024 128/256/512/1024/2048 并行度 8 1 1 8 數(shù)據(jù)類型：字長 (bit) 塊浮點：12 浮點：32 定點：16 浮點：32/浮點：16 平均輸出SQNR (dB) 57 139 55 SP：135/HP：60 時鐘頻率 (MHz) 324 400 200 435 計算時間 (μs) 0.3 2.6 5.1 0.2/0.3/0.6/1.1/2.2 運算吞吐率 (MSample/s) 2592 400 200 SP：3478/HP：6957 平均功耗 (mW) 42 417 8 104 @435 MHz 有效面積 (mm2) 0.93 1.19 0.15 1.41 歸一化面積 10.0 22.1 1.9 16.0 歸一化吞吐率面積比 259 18 103 SP：220/HP：440
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