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基于存儲(chǔ)劃分和路徑重用的粗粒度可重構(gòu)結(jié)構(gòu)循環(huán)映射算法

張興明 袁開堅(jiān) 高彥釗

張興明, 袁開堅(jiān), 高彥釗. 基于存儲(chǔ)劃分和路徑重用的粗粒度可重構(gòu)結(jié)構(gòu)循環(huán)映射算法[J]. 電子與信息學(xué)報(bào), 2018, 40(6): 1520-1524. doi: 10.11999/JEIT170748
引用本文: 張興明, 袁開堅(jiān), 高彥釗. 基于存儲(chǔ)劃分和路徑重用的粗粒度可重構(gòu)結(jié)構(gòu)循環(huán)映射算法[J]. 電子與信息學(xué)報(bào), 2018, 40(6): 1520-1524. doi: 10.11999/JEIT170748
ZHANG Xingming, YUAN Kaijian, GAO Yanzhao. Coarse Grained Reconfigurable Architecture Loop Mapping Algorithm Based on Memory Partitioning and Path Reuse[J]. Journal of Electronics & Information Technology, 2018, 40(6): 1520-1524. doi: 10.11999/JEIT170748
Citation: ZHANG Xingming, YUAN Kaijian, GAO Yanzhao. Coarse Grained Reconfigurable Architecture Loop Mapping Algorithm Based on Memory Partitioning and Path Reuse[J]. Journal of Electronics & Information Technology, 2018, 40(6): 1520-1524. doi: 10.11999/JEIT170748

基于存儲(chǔ)劃分和路徑重用的粗粒度可重構(gòu)結(jié)構(gòu)循環(huán)映射算法

doi: 10.11999/JEIT170748
基金項(xiàng)目: 

國(guó)家科技重大專項(xiàng)(2016ZX01012101),國(guó)家自然科學(xué)基金(61572520, 61521003)

Coarse Grained Reconfigurable Architecture Loop Mapping Algorithm Based on Memory Partitioning and Path Reuse

Funds: 

The National Science Technology Major Project (2016ZX01012101), The National Natural Science Foundation of China (61572520, 61521003)

  • 摘要: 目前針對(duì)粗粒度可重構(gòu)結(jié)構(gòu)循環(huán)映射的研究主要集中在操作布局和臨時(shí)數(shù)據(jù)路由,缺乏考慮數(shù)據(jù)映射的研究,該文提出一種基于存儲(chǔ)劃分和路徑重用的模調(diào)度映射流程。首先進(jìn)行細(xì)粒度的存儲(chǔ)劃分找到合適的數(shù)據(jù)映射,提高數(shù)據(jù)存取的并行性,再用模調(diào)度尋找操作布局和臨時(shí)數(shù)據(jù)路由,最后利用構(gòu)建的路由開銷模型平衡存儲(chǔ)器路由和處理單元路由的使用,引入路徑重用策略優(yōu)化路由資源。實(shí)驗(yàn)結(jié)果表明,該方法在循環(huán)的啟動(dòng)間隔、每周期指令數(shù)和執(zhí)行延遲等方面均具有良好的性能。
  • PAGER J, JEYAPAUL R, and SHRIVASTAVA A. A software scheme for multithreading on CGRAs[J]. ACM Transactions on Embedded Computing Systems, 2015, 14(1): 19:1-19:26. doi: 10.1145/2638558.
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    YIN S, YAO X, LIU D, et al. Memory-aware loop mapping on coarse-grained reconfigurable architectures[J]. IEEE Transactions on Very Large Scale Integration Systems, 2016, 24(5): 1895-1908. doi: 10.1109/TVLSI.2015.2474129.
    THEOCHARIS P and SUTTER B. A bimodal scheduler for coarse-grained reconfigurable arrays[J]. ACM Transactions on Architecture and Code Optimization, 2016, 13(2): 15:1-15:26. doi: 10.1145/2893475.
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    KIM Y, LEE J, SHRIVASTAVA A, et al. High throughput data mapping for coarse-grained reconfigurable architectures[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011, 30(11): 1599-1609. doi: 10.1109/TCAD.2011.2161217.
    SU J, YANG F, ZENG X, et al. Efficient memory partitioning for parallel data access via data reuse[C]. ACM /SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, USA, 2016: 138-147. doi: 10.1145/ 2847263.2847264.
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    MUKHERJEE M, FELL A, and GUHA A. DFGenTool: A dataflow graph generation tool for coarse grain reconfigurable architectures[C]. International Conference on VLSI Design, Hyderabad, India, 2017: 67-72. doi: 10.1109/VLSID.2017.62.
    陳銳, 楊海鋼, 王飛, 等. 基于自路由互連網(wǎng)絡(luò)的粗粒度可重構(gòu)陣列結(jié)構(gòu)[J]. 電子與信息學(xué)報(bào), 2014, 36(9): 2251-2257. doi: 10.3724/SP.J.1146.2013.01646.
    CHEN Rui, YANG Haigang, WANG Fei, et al. Coarse- grained reconfigurable array based on self-routing interconnection network[J]. Journal of Electronics Information Technology, 2014, 36(9): 2251-2257. doi: 10.3724 /SP.J.1146.2013.01646.
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出版歷程
  • 收稿日期:  2017-07-21
  • 修回日期:  2017-12-18
  • 刊出日期:  2018-06-19

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