面向全同態(tài)加密的有限域FFT算法FPGA設(shè)計(jì)

施佺; 韓賽飛; 黃新明; 孫玲; 謝星; 唐天澤

doi:10.11999/JEIT170312

面向全同態(tài)加密的有限域FFT算法FPGA設(shè)計(jì)

doi: 10.11999/JEIT170312

1.
(南通大學(xué)電子信息學(xué)院南通 226019) ②(江蘇省專用集成電路設(shè)計(jì)重點(diǎn)實(shí)驗(yàn)室南通 226019)

基金項(xiàng)目:

國家自然科學(xué)基金(61571246)，南通大學(xué)杏林學(xué)院自然科學(xué)基金(13010538)

計(jì)量
- 文章訪問數(shù): 2393
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- 被引次數(shù): 0
出版歷程
- 收稿日期: 2017-04-10
- 修回日期: 2017-07-19
- 刊出日期: 2018-01-19

Design of Finite Field FFT for Fully Homomorphic Encryption Based on FPGA

1.
(School of Electronic Information, Nantong University, Nantong 226019, China)

Funds:

The National Natural Science Foundation of China (61571246), The Natural Science Foundation of Xinglin College of Nantong University (13010538)

摘要

摘要: 大數(shù)乘法是全同態(tài)加密算法中一個(gè)不可或缺的單元模塊，也是其中耗時(shí)最多的模塊，設(shè)計(jì)一個(gè)性能優(yōu)良的大數(shù)乘法器有助于推進(jìn)全同態(tài)加密的實(shí)用化進(jìn)程。針對SSA大數(shù)乘法器的實(shí)現(xiàn)需求，該文采用可綜合Verilog HDL語言完成了一個(gè)1624 bit有限域FFT算法的FPGA設(shè)計(jì)，通過構(gòu)建樹型大數(shù)求和單元和并行化處理方法有效提高了FFT算法的速度。與VIM編譯環(huán)境下的系統(tǒng)級仿真結(jié)果比較，驗(yàn)證了有限域FFT算法FPGA設(shè)計(jì)的正確性。
- 全同態(tài)加密 /
- 大數(shù)乘法 /
- 有限域快速傅里葉變換 /
- 現(xiàn)場可編程門陣列
Abstract: Large multiplier is an indispensable module in fully homomorphic encryption, while is also the most time-consuming module. Therefore, design of a large multiplier with good performance is help to promote the practical process of fully homomorphic encryption. Aimed at the demand of SSA (Sch?nhage-Strassen Algorithm) large multiplier, a 1624 bit finite field FFT based on FPGA is designed by using Verilog HDL language. By constructing the tree type large sum unit and using parallel processing method, the speed of FFT algorithm is improved effectively. And its correctness is proved by comparing with the system level simulation results in VIM compiler environment.
- Fully homomorphic encryption /
- Large multiplier /
- Finite field FFT /
- Field Programmable Gate Array (FPGA)

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參考文獻(xiàn)(24)

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