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面向密碼算法的大位寬比特置換操作高速實(shí)現(xiàn)方案

戴紫彬,  馬超,  李偉,  南龍梅

戴紫彬, 馬超, 李偉, 南龍梅. 面向密碼算法的大位寬比特置換操作高速實(shí)現(xiàn)方案[J]. 電子與信息學(xué)報(bào), 2017, 39(9): 2119-2126. doi: 10.11999/JEIT161285
引用本文: 戴紫彬, 馬超, 李偉, 南龍梅. 面向密碼算法的大位寬比特置換操作高速實(shí)現(xiàn)方案[J]. 電子與信息學(xué)報(bào), 2017, 39(9): 2119-2126. doi: 10.11999/JEIT161285
DAI Zibin, MA Chao, LI Wei, NAN Longmei. Wide-width Bit Permutation Instructions for Accelerating Cryptographic Algorithms[J]. Journal of Electronics & Information Technology, 2017, 39(9): 2119-2126. doi: 10.11999/JEIT161285
Citation: DAI Zibin, MA Chao, LI Wei, NAN Longmei. Wide-width Bit Permutation Instructions for Accelerating Cryptographic Algorithms[J]. Journal of Electronics & Information Technology, 2017, 39(9): 2119-2126. doi: 10.11999/JEIT161285

面向密碼算法的大位寬比特置換操作高速實(shí)現(xiàn)方案

doi: 10.11999/JEIT161285
  • 1.

    (解放軍信息工程大學(xué) 鄭州 450001) ②(復(fù)旦大學(xué)專用集成電路與系統(tǒng)國(guó)家重點(diǎn)實(shí)驗(yàn)室 上海 200433)

基金項(xiàng)目: 

國(guó)家自然科學(xué)基金(61404175)

Wide-width Bit Permutation Instructions for Accelerating Cryptographic Algorithms

  • 1.

    (The PLA Information Engineering University, Zhengzhou 450001, China)

  • 2.

    (State Key Laboratory of ASIC and System, Fudan University, Shanghai 200433, China)

Funds: 

The National Natural Science Foundation of China (61404175)

  • 摘要: 針對(duì)面向字級(jí)優(yōu)化的通用處理器，在應(yīng)對(duì)密碼算法中大位寬比特置換操作時(shí)效率較低的問題，該文提出2N-2N和kN-kN(k2)的大位寬比特置換操作高速實(shí)現(xiàn)方案。并針對(duì)方案中涉及的比特提取和比特提取-移位兩種操作，分別提出專用擴(kuò)展指令BEX, BEX-ROT。在此基礎(chǔ)上，對(duì)專用指令硬件架構(gòu)的高效設(shè)計(jì)進(jìn)行研究，提出一種基于Inverse Butterfly網(wǎng)絡(luò)統(tǒng)一硬件架構(gòu)-RERS(Reconfigurable Extract and Rotation Shifter)及相應(yīng)可重構(gòu)路由算法，以最大限度地共享硬件資源，減小電路面積。實(shí)驗(yàn)結(jié)果表明，所提方案能夠?qū)⑻幚砥骷軜?gòu)執(zhí)行大位寬比特置換操作的指令條數(shù)縮減約10倍，大幅提升其處理效率。同時(shí)，由專用指令所帶來的硬件資源開銷和延遲開銷均較低，不會(huì)影響到原架構(gòu)正常工作頻率。
    Abstract: Wide-width bit permutation is a very commonly used operation in symmetric cryptographic algorithms. However, current word-oriented general microprocessors are inefficient to cope with the complex bit-level permutation operations. To solve this problem, two schemes for 2N-2N and kN-kN permutations are proposed respectively, including two extended instructions BEX and BEX-ROT. Furthermore, the efficient hardware implementation of the instructions are studied, and then a unified hardware circuit named RERS (Reconfigurable Extract and Rotation Shifter) is proposed with a corresponding reconfigurable routing algorithm. The RERS can share hardware resources to achieve the purpose of reducing area. The experimental results show that the proposed schemes can truly decrease the number of instructions for accomplishing an arbitrary wide-width bit permutation (instructions reduced by 10 times), which greatly accelerate the performance of microprocessors. At the same time, the overhead of hardware resources and delay caused by the two extended instructions is very low, which will not affect the normal operating frequency of the original microprocessors.
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出版歷程
  • 收稿日期:  2016-11-25
  • 修回日期:  2017-06-05
  • 刊出日期:  2017-09-19

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