一種高效的混合Test-Per-Clock測試方法

劉鐵橋; 牛小燕; 楊潔; 毛峰

doi:10.11999/JEIT161202

一種高效的混合Test-Per-Clock測試方法

doi: 10.11999/JEIT161202

基金項(xiàng)目:

浙江省自然科學(xué)基金(LQ15F040005)

計(jì)量
- 文章訪問數(shù): 1109
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- 被引次數(shù): 0
出版歷程
- 收稿日期: 2016-11-08
- 修回日期: 2017-04-10
- 刊出日期: 2017-09-19

An Efficient Mixed-mode Test-Per-Clock Scheme

Funds:

Zhejiang Provincial Natural Science Foundation (LQ15F040005)

摘要

摘要: 該文提出了一種基于內(nèi)建自測試(BIST)的Test-Per-Clock混合模式向量產(chǎn)生方法。測試由兩個部分組成：自由線性反饋移位寄存器(LFSR)偽隨機(jī)測試模式和受控LFSR確定型測試模式。偽隨機(jī)測試模式用于快速地檢測偽隨機(jī)易測故障，減少確定型數(shù)據(jù)存儲。受控LFSR測試模式采用直接存儲在ROM中的控制位流對剩余故障產(chǎn)生確定型測試。通過對提出的BIST混合模式測試結(jié)構(gòu)理論分析，提出了偽隨機(jī)向量的選取方法以及基于受控線性移位確定型測試生成方法?；鶞?zhǔn)電路的仿真結(jié)果表明，該方法可以獲得完全單固定型故障覆蓋率，其測試產(chǎn)生器設(shè)計(jì)簡單且具有良好的穩(wěn)定性，與其他方法相比，具有較低的測試開銷和較短的測試應(yīng)用時間。
- IC測試 /
- 內(nèi)建自測試 /
- Test-Per-Clock測試 /
- 測試生成
Abstract: A mixed-mode Test-Per-Clock Built In Self Test (BIST) scheme is proposed. The test consists of two parts: the free Linear Feedback Shift Register (LFSR) pseudo-random test mode and the deterministic test pattern based on controlled LFSR. Pseudo random test mode is used to quickly detect pseudo-random susceptible faults and reduce the deterministic data storage. Controlled LFSR test mode uses the control bits directly stored in the ROM to generate a deterministic test of the remaining faults. Based on the theoretical analysis of the proposed mixed-mode BIST test structure, a pseudo-random test sequence selection method and a deterministic test generation method based on controlled linear shifter are proposed. Simulation results on benchmark circuits show that the proposed method can obtain the complete single stuck-at fault coverage and has good stability in test generation. Compared with other methods, it has simpler Test Pattern Generator (TPG) design and lower test cost as well as shorter test application time.
- IC test /
- Built In Self Test (BIST) /
- Test-Per-Clock test /
- Test generation

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