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考慮偏置溫度不穩(wěn)定性的軟差錯率分析

王真,  江建慧,  陳乃金

王真, 江建慧, 陳乃金. 考慮偏置溫度不穩(wěn)定性的軟差錯率分析[J]. 電子與信息學(xué)報, 2017, 39(7): 1640-1645. doi: 10.11999/JEIT161113
引用本文: 王真, 江建慧, 陳乃金. 考慮偏置溫度不穩(wěn)定性的軟差錯率分析[J]. 電子與信息學(xué)報, 2017, 39(7): 1640-1645. doi: 10.11999/JEIT161113
WANG Zhen, JIANG Jianhui, CHEN Naijin. Bias Temperature Instability-aware Soft Error Rate Analysis[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1640-1645. doi: 10.11999/JEIT161113
Citation: WANG Zhen, JIANG Jianhui, CHEN Naijin. Bias Temperature Instability-aware Soft Error Rate Analysis[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1640-1645. doi: 10.11999/JEIT161113

考慮偏置溫度不穩(wěn)定性的軟差錯率分析

doi: 10.11999/JEIT161113
基金項目: 

國家自然科學(xué)基金(61432017, 61404092)，上海電力學(xué)院人才啟動基金(K-2013-017)，上海高校青年教師資助計劃項目(Z2015-074)，上海市科委地方能力建設(shè)項目(15110500700)

Bias Temperature Instability-aware Soft Error Rate Analysis

Funds: 

The National Natural Science Foundation of China (61432017, 61404092), The Talented People Introduction Foundation of Shanghai University of Electric Power (K-2013-017), The Excellent University Young Teachers Training Program of Shanghai Municipal Education Commission (Z2015-074), The Project of Shanghai Science and Technology Committee Grant (15110500700)

  • 摘要: 納米工藝下，老化效應(yīng)與軟差錯共同引發(fā)的集成電路可靠性問題至關(guān)重要。該文分析偏置溫度不穩(wěn)定性(BTI)，包括負偏置溫度不穩(wěn)定性(NBTI)和正偏置溫度不穩(wěn)定性(PBTI)對軟差錯率的影響，提出從關(guān)鍵電荷值和延遲兩個因素綜合考慮。首先分析BTI效應(yīng)下兩個因素如何變化，推導(dǎo)了延遲受BTI影響的變化模型，介紹關(guān)鍵電荷的變化機理。然后探討將兩個因素結(jié)合到軟差錯率(SER)評估中，推導(dǎo)了融入關(guān)鍵電荷值的SER計算模型，提出將延遲的變化導(dǎo)入到電氣屏蔽中的方法?；贗SCAS89基準(zhǔn)電路上的實驗驗證了綜合兩種因素考慮BTI效應(yīng)評估SER的有效性和準(zhǔn)確性。
    Abstract: Under nano-scaled technology, the Integrated Circuit (IC) reliability issues caused by both aging mechanism and soft error become very critical. In this paper, from critical charge and delay points of view, the effects of Bias Temperature Instability (BTI), including Negative BTI (NBTI) and Positive BTI (PBTI), on Soft Error Rate (SER) are analyzed. Firstly, how BTI affects critical charge and delay is focused on. The delay increasing model is derived, and the critical charge changing procedure is introduced. Further, using the derived SER computational model considering critical charge, and mapping the changed delay into electrical mask procedure, the SER is accurately calculated. Experimental results on ISCAS89 benchmark circuits show that, considering two factors of BTI, SER estimation has high accuracy.
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出版歷程
  • 收稿日期:  2016-10-20
  • 修回日期:  2017-03-23
  • 刊出日期:  2017-07-19

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