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基于概率CMOS模型的反饋環(huán)路的數(shù)字電路容錯特性分析

李妍 胡劍浩 楊澤國

李妍, 胡劍浩, 楊澤國. 基于概率CMOS模型的反饋環(huán)路的數(shù)字電路容錯特性分析[J]. 電子與信息學(xué)報, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096
引用本文: 李妍, 胡劍浩, 楊澤國. 基于概率CMOS模型的反饋環(huán)路的數(shù)字電路容錯特性分析[J]. 電子與信息學(xué)報, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096
LI Yan, HU Jianhao, YANG Zeguo. Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096
Citation: LI Yan, HU Jianhao, YANG Zeguo. Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model[J]. Journal of Electronics & Information Technology, 2017, 39(7): 1634-1639. doi: 10.11999/JEIT161096

基于概率CMOS模型的反饋環(huán)路的數(shù)字電路容錯特性分析

doi: 10.11999/JEIT161096
基金項目: 

國家自然科學(xué)基金(61371104)

Fault-tolerant Analysis for Feedback Based Digital Circuit via Probabilistic CMOS Model

Funds: 

The National Natural Science Foundation of China (61371104)

  • 摘要: 反饋環(huán)路是模擬電路中有效容錯的電路結(jié)構(gòu)。反饋電路也因其存儲性能而被廣泛使用于數(shù)字電路的時序電路中,但是反饋電路在數(shù)字電路的組合電路的穩(wěn)定特性鮮少被人研究,尤其是低功耗應(yīng)用。以馬氏隨機(jī)場為理論的MRF電路以其低功耗下的高穩(wěn)定性得到研究和關(guān)注,但其電路的反饋結(jié)構(gòu)缺乏理論支持和依據(jù),因此馬氏隨機(jī)場電路的容錯特性未被清晰得以解釋。該文以利用概率CMOS建模概率門來分析MRF核心反饋環(huán)NAND-NAND,從理論上證明了反饋電路輸出的計算正確概率具有遞增且上有界的特點,并數(shù)學(xué)證明了MRF的核心反饋環(huán)電路具有優(yōu)于傳統(tǒng)CMOS電路的容錯性能。其理論推導(dǎo)結(jié)果與測試結(jié)果呈現(xiàn)一致性。
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  • 文章訪問數(shù):  1025
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  • 被引次數(shù): 0
出版歷程
  • 收稿日期:  2016-10-17
  • 修回日期:  2017-01-24
  • 刊出日期:  2017-07-19

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