40 nm CMOS工藝下的低功耗容軟錯(cuò)誤鎖存器

黃正峰; 王世超; 歐陽一鳴; 易茂祥; 梁華國(guó)

doi:10.11999/JEIT160889

40 nm CMOS工藝下的低功耗容軟錯(cuò)誤鎖存器

doi: 10.11999/JEIT160889

1.
(合肥工業(yè)大學(xué)電子科學(xué)與應(yīng)用物理學(xué)院合肥 230009) ②(合肥工業(yè)大學(xué)計(jì)算機(jī)與信息學(xué)院合肥 230009)

基金項(xiàng)目:

國(guó)家自然科學(xué)基金(61574052, 61371025, 61474036, 61674048)，安徽省自然科學(xué)基金(1608085MF149)

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- 文章訪問數(shù): 1383
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- 被引次數(shù): 0
出版歷程
- 收稿日期: 2016-09-02
- 修回日期: 2017-02-22
- 刊出日期: 2017-06-19

Low Power Soft Error Tolerant Latch for 40 nm CMOS Technology

1.
(School of Electronic Science &
2.
(School of Computer &

Funds:

The National Natural Science Foundation of China (61574052, 61371025, 61474036, 61674048), The Natural Science Foundation of Anhui Province (1608085MF149)

摘要

摘要: 為了降低集成電路的軟錯(cuò)誤率，該文基于時(shí)間冗余的方法提出一種低功耗容忍軟錯(cuò)誤鎖存器。該鎖存器不但可以過濾上游組合邏輯傳播過來的SET脈沖，而且對(duì)SEU完全免疫。其輸出節(jié)點(diǎn)不會(huì)因?yàn)楦吣芰Ｗ愚Z擊而進(jìn)入高阻態(tài)，所以該鎖存器能夠適用于門控時(shí)鐘電路。SPICE仿真結(jié)果表明，與同類的加固鎖存器相比，該文結(jié)構(gòu)僅僅增加13.4%的平均延時(shí)，使得可以過濾的SET脈沖寬度平均增加了44.3%，并且功耗平均降低了48.5%，功耗延時(shí)積(PDP)平均降低了46.0%，晶體管數(shù)目平均減少了9.1%。
- 軟錯(cuò)誤 /
- 單粒子翻轉(zhuǎn) /
- 單粒子瞬態(tài) /
- 加固鎖存器
Abstract: To reduce the soft error rate of the circuit, this paper proposes a low power soft error tolerant latch based on time redundancy technology. The proposed latch can fully tolerate the Single Event Upset (SEU) when particles strike on internal nodes. Furthermore, it can efficiently mask the input Single Event Transient (SET). Its output node will not enter a high impedance state when a particle strikes on internal nodes, so the proposed latch can be applied to clock-gating circuits. Detailed SPICE simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures. Compared with other soft error tolerant latches, the proposed latch introduces 13.4% delay overhead on average. While it can achieve 44.3% increase in filterable SET pulse width, 48.5% reduction in power, 46.0% reduction in Power Delay Product (PDP), and 9.1% reduction in transistor numbers on average.
- Soft error /
- Single Event Upset (SEU) /
- Single Event Transient (SET) /
- Hardened latch

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參考文獻(xiàn)(26)

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