一级黄色片免费播放|中国黄色视频播放片|日本三级a|可以直接考播黄片影视免费一级毛片

高級(jí)搜索

留言板

尊敬的讀者、作者、審稿人, 關(guān)于本刊的投稿、審稿、編輯和出版的任何問題, 您可以本頁添加留言。我們將盡快給您答復(fù)。謝謝您的支持!

姓名
郵箱
手機(jī)號(hào)碼
標(biāo)題
留言內(nèi)容
驗(yàn)證碼

40 nm CMOS工藝下的低功耗容軟錯(cuò)誤鎖存器

黃正峰 王世超 歐陽一鳴 易茂祥 梁華國(guó)

黃正峰, 王世超, 歐陽一鳴, 易茂祥, 梁華國(guó). 40 nm CMOS工藝下的低功耗容軟錯(cuò)誤鎖存器[J]. 電子與信息學(xué)報(bào), 2017, 39(6): 1464-1471. doi: 10.11999/JEIT160889
引用本文: 黃正峰, 王世超, 歐陽一鳴, 易茂祥, 梁華國(guó). 40 nm CMOS工藝下的低功耗容軟錯(cuò)誤鎖存器[J]. 電子與信息學(xué)報(bào), 2017, 39(6): 1464-1471. doi: 10.11999/JEIT160889
HUANG Zhengfeng, WANG Shichao, OUYANG Yiming, YI Maoxiang, LIANG Huaguo. Low Power Soft Error Tolerant Latch for 40 nm CMOS Technology[J]. Journal of Electronics & Information Technology, 2017, 39(6): 1464-1471. doi: 10.11999/JEIT160889
Citation: HUANG Zhengfeng, WANG Shichao, OUYANG Yiming, YI Maoxiang, LIANG Huaguo. Low Power Soft Error Tolerant Latch for 40 nm CMOS Technology[J]. Journal of Electronics & Information Technology, 2017, 39(6): 1464-1471. doi: 10.11999/JEIT160889

40 nm CMOS工藝下的低功耗容軟錯(cuò)誤鎖存器

doi: 10.11999/JEIT160889
基金項(xiàng)目: 

國(guó)家自然科學(xué)基金(61574052, 61371025, 61474036, 61674048),安徽省自然科學(xué)基金(1608085MF149)

Low Power Soft Error Tolerant Latch for 40 nm CMOS Technology

Funds: 

The National Natural Science Foundation of China (61574052, 61371025, 61474036, 61674048), The Natural Science Foundation of Anhui Province (1608085MF149)

  • 摘要: 為了降低集成電路的軟錯(cuò)誤率,該文基于時(shí)間冗余的方法提出一種低功耗容忍軟錯(cuò)誤鎖存器。該鎖存器不但可以過濾上游組合邏輯傳播過來的SET脈沖,而且對(duì)SEU完全免疫。其輸出節(jié)點(diǎn)不會(huì)因?yàn)楦吣芰W愚Z擊而進(jìn)入高阻態(tài),所以該鎖存器能夠適用于門控時(shí)鐘電路。SPICE仿真結(jié)果表明,與同類的加固鎖存器相比,該文結(jié)構(gòu)僅僅增加13.4%的平均延時(shí),使得可以過濾的SET脈沖寬度平均增加了44.3%,并且功耗平均降低了48.5%,功耗延時(shí)積(PDP)平均降低了46.0%,晶體管數(shù)目平均減少了9.1%。
  • ROBERT L. S. Porting and scaling strategies for nanoscale CMOS RHBD[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2015, 62(12): 2856-2863. doi: 10.1109/TCSI.2015.2495779.
    黃正峰, 陳凡, 蔣翠云, 等. 基于時(shí)序優(yōu)先的電路容錯(cuò)混合加固方案[J]. 電子與信息學(xué)報(bào), 2014, 36(1): 234-240. doi: 10.3724/SP.J.1146.2013.00449.
    HUANG Zhengfeng, CHEN Fan, JIANG Cuiyun, et al. A hybrid hardening strategy for circuit soft-error-tolerance based on timing priority[J]. Journal of Electronics Information Technology, 2014, 36(1): 234-240. doi: 10.3724/ SP.J.1146.2013.00449.
    ARTOLA L, GAILLARDIN M. HUBERT G, et al. Modeling single event transients in advanced devices and ICs[J]. IEEE Transactions on Nuclear Science, 2015, 62(4): 1528-1539. doi: 10.1109/TNS.2015.2432271.
    VRONIQUE F C, LLOYD W M, and PASCAL G. Single event transients in digital CMOSA review[J]. IEEE Transactions on Nuclear Science, 2013, 60(3): 1767-1790. doi: 10.1109/TNS.2013.2255624.
    NEALE A and SACHDEV M. Neutron radiation induced soft error rates for an adjacent-ECC protected SRAM in 28 nm CMOS[J]. IEEE Transactions on Nuclear Science, 2016, 63(3): 1912-1917. doi: 10.1109/TNS.2016.2547963.
    NEALE A, JONKMAN M, and SACHDEV M. Adjacent- MBU-tolerant SECDED-TAEC-yAED codes for embedded SRAMs[J]. IEEE Transactions on Circuits and System-II Express Brifs, 2015, 62(4): 387-391. doi: 10.1109/TCSII.2014. 2368262.
    CALIN T, NICOLAIDIS M, and VELAZCO R. Upset hardened memory design for submicron cmos technology[J]. IEEE Transactions on Nuclear Science, 1996, 43(6): 2874-2878. doi: 10.1109/23.556880.
    CASEY M C, BHUVA B L, BLACK J D, et al. HBD using cascade-voltage switch logic gates for SET tolerant digital designs[J]. IEEE Transactions on Nuclear Science, 2005, 52(6): 2510-2515. doi: 10.1109/TNS.2005.860715.
    SASAKI Y, NAMBA K, and ITO H. Circuit and latch capable of masking soft errors with Schmitt trigger[J]. Journal of Electronic Testing, 2008, 24(1~3): 11-19. doi: 10.1007/s10836-007-5034-2.
    NICOLAIDIS M. Design for soft error mitigation[J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3): 405-418. doi: 10.1109/TDMR.2005.855790.
    REN Yi, CHEN Li, and BI Jinshun. An RHBD bandgap reference utilizing single event transient isolation technique[J]. IEEE Transactions on Nuclear Science, 2016, 63(3): 1927-1933. doi: 10.1109/TNS.2016.2554104.
    MAVIS D G and EATON P H. Soft error rate mitigation techniques for modern microcircuits[C]. Proceedings of 2002 IEEE International Reliability Physics Symposium, Dallas, TX, USA, 2002: 216-225.
    ZHANG M, MITRA S, MAK T M, et al. Sequential element design with built-in soft error resilience[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006, 14(12): 1368-1378. doi: 10.1109/TVLSI.2006.887832.
    LIN S, KIM Y B, and LOMBARDI F. Soft-error hardening designs of nanoscale cmos latches[C]. Proceedings of 27th IEEE VLSI Test Symposium, Santa Cruz, CA, USA, 2009: 41-46.
    QI C, XIAO L, GUO J, et al. Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology [J]. Microelectronics Reliability, 2015, 55(6): 863-872 . doi: 10.1016/j.microrel.2015.03.014.
    OMANA M, ROSSI D, and METRA C. Latch susceptibility to transient faults and new hardening approach[J]. IEEE Transactions on Computers, 2007, 56(9): 1255-1268. doi: 10. 1109/TC.2007.1070.
    HOSSEIN K A and VOJIN G O. Low-power soft error hardened latch[J]. Journal of Low Power Electronics, 2010, 6(1): 1-9. doi: 10.1007/978-3-642-11802-9_30.
    SAEIDEH S and RAHEBEH N A. A novel soft error hardened latch design in 90nm CMOS[C]. Proceedings of the 16th CSI International Symposium on Computer Architecture and Digital Systems, Shiraz, Iran, 2012: 60-63.
    RAJAEI R, TABANDEH M, and FAZELI M. Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation[J]. Microelectronics Reliability, 2013, 53(6): 912-924. doi: 10.1016/j.microrel.2013. 02.012.
    HUANG Zhengfeng, LIANG Huaguo, and HELLEBRAND S. A high performance SEU tolerant latch[J]. Journal of Electronic Testing. 2015, 31(4): 349-359. doi: 10.1007/s10836 -015-5533-5.
    JUN F, JUNKI Y, and KAZUTOSHI K. A radiation- hardened non-redundant flip-flop, stacked leveling critical charge flip-flop in a 65 nm thin BOX FD-SOI process[J]. IEEE Transactions on Nuclear Science, 2016, 63(4): 2080-2086. doi: 10.1109/TNS.2016.2543745.
    LU Y, LOMBARDI F, PONTARELLI S, et al. Design and analysis of single-event tolerant slave latches for enhanced scan delay testing[J]. IEEE Transactions on Device and Materials Reliability, 2014, 14(1): 333-343. doi: 10.1109/ TDMR.2013.2266543.
    MESSENGER G C. Collection of charge on junction nodes from ion tracks[J]. IEEE Transactions on Nuclear Science, 1982, 29(6): 2024-2031. doi: 10.1109/TNS.1982.4336490.
    NAN H and CHOI K. High performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2012, 59(7): 1445-1457. doi: 10.1109/TCSI. 2011.2177135.
    YAN Aibin, LIANG Huaguo, HUANG Zhengfeng, et al. An SEU resilient, SET filterable and cost effective latch in presence of PVT variations[J]. Microelectronics Reliability, 2016, 63(1): 239-250. doi: 10.1016/j.microrel.2016.06.004.
  • 加載中
計(jì)量
  • 文章訪問數(shù):  1383
  • HTML全文瀏覽量:  179
  • PDF下載量:  491
  • 被引次數(shù): 0
出版歷程
  • 收稿日期:  2016-09-02
  • 修回日期:  2017-02-22
  • 刊出日期:  2017-06-19

目錄

    /

    返回文章
    返回