高性能集成鎖相環(huán)中低失配電荷泵的設(shè)計(jì)

施展; 余雋; 唐禎安; 蔡泓; 馮沖

doi:10.11999/JEIT160826

高性能集成鎖相環(huán)中低失配電荷泵的設(shè)計(jì)

doi: 10.11999/JEIT160826

施展¹,
余雋¹,
唐禎安¹,
蔡泓¹,
馮沖²

1.
(大連理工大學(xué)電子科學(xué)與技術(shù)學(xué)院大連 116024) ②(大連民族大學(xué)信息與通信工程學(xué)院大連 116600

基金項(xiàng)目:

國家自然科學(xué)基金(61131004, 61274076, 61001054)

計(jì)量
- 文章訪問數(shù): 1473
- HTML全文瀏覽量: 166
- PDF下載量: 343
- 被引次數(shù): 0
出版歷程
- 收稿日期: 2016-08-03
- 修回日期: 2017-02-08
- 刊出日期: 2017-06-19

Design of a Low-spur Charge Pump for High Performance CMOS Phase-locked Loops

1.
(School of Electronic Science and Technology, Dalian University of Technology, Dalian 116024, China)

Funds:

The National Natural Science Foundation of China (61131004, 61274076, 61001054)

摘要

摘要: 在分析電荷泵結(jié)構(gòu)、工作原理和產(chǎn)生雜散機(jī)理的基礎(chǔ)上，該文提出了一種低靜態(tài)電流失配、低時(shí)序失配的高性能電荷泵。此電荷泵通過減小電荷泵開關(guān)過程中時(shí)序失配和電流失配，減小了高頻鎖相環(huán)中的抖動(dòng)和雜散?；谥行緡H0.18 m CMOS射頻工藝技術(shù)和1.8 V電源電壓，對采用此高性能電荷泵的鎖相環(huán)進(jìn)行了相位噪聲仿真。仿真結(jié)果驗(yàn)證了這些鎖相環(huán)具有低噪聲特性：在480 MHz的輸出頻率下，二階鎖相環(huán)的周期抖動(dòng)為1.05 ps，最大參考雜散為-121 dBc。
- 集成電路 /
- 鎖相環(huán) /
- 抖動(dòng) /
- 參考雜散
Abstract: On the basis of the analysis of the structure, operation principle and mechanism of generating spurs of the charge pump, a charge pump with a low static current mismatch and a low timing mismatch is proposed. This charge pump suppresses the jitter and spurs in high-speed Phase-Looked Loops (PLL) by improving the timing mismatch and the current mismatch during switching in the charge pump. Based on the SMIC 0.18 m CMOS radio frequency technology with 1.8 V power supply, the phase noise simulation of the PLLs adopting the proposed charge pump is performed. The simulation results demonstrate that those PLLs achieve a low noise performance: the second-order PLL shows a period jitter of 1.05 ps and the largest reference spur of -121 dBc with the PLL output frequency of 480 MHz.
- Integrated Circuits (IC) /
- Phase-Locked Loop (PLL) /
- Jitter /
- Reference spur

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