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條件推測性十進(jìn)制加法器的優(yōu)化設(shè)計(jì)

崔曉平,  王書敏,  劉偉強(qiáng),  董文雯

崔曉平, 王書敏, 劉偉強(qiáng), 董文雯. 條件推測性十進(jìn)制加法器的優(yōu)化設(shè)計(jì)[J]. 電子與信息學(xué)報(bào), 2016, 38(10): 2689-2694. doi: 10.11999/JEIT151416
引用本文: 崔曉平, 王書敏, 劉偉強(qiáng), 董文雯. 條件推測性十進(jìn)制加法器的優(yōu)化設(shè)計(jì)[J]. 電子與信息學(xué)報(bào), 2016, 38(10): 2689-2694. doi: 10.11999/JEIT151416
CUI Xiaoping, WANG Shumin, LIU Weiqiang, DONG Wenwen. Design of Optimized Conditional Speculative Decimal Adders CUI Xiaoping WANG Shumin LIU Weiqiang DONG Wenwen[J]. Journal of Electronics & Information Technology, 2016, 38(10): 2689-2694. doi: 10.11999/JEIT151416
Citation: CUI Xiaoping, WANG Shumin, LIU Weiqiang, DONG Wenwen. Design of Optimized Conditional Speculative Decimal Adders CUI Xiaoping WANG Shumin LIU Weiqiang DONG Wenwen[J]. Journal of Electronics & Information Technology, 2016, 38(10): 2689-2694. doi: 10.11999/JEIT151416

條件推測性十進(jìn)制加法器的優(yōu)化設(shè)計(jì)

doi: 10.11999/JEIT151416

Design of Optimized Conditional Speculative Decimal Adders CUI Xiaoping WANG Shumin LIU Weiqiang DONG Wenwen

  • 摘要: 隨著商業(yè)計(jì)算和金融分析等高精度計(jì)算應(yīng)用領(lǐng)域的高速發(fā)展，提供硬件支持十進(jìn)制算術(shù)運(yùn)算變得越來越重要，新的IEEE 754-2008浮點(diǎn)運(yùn)算標(biāo)準(zhǔn)也添加了十進(jìn)制算術(shù)運(yùn)算規(guī)范。該文采用目前最佳的條件推測性算法設(shè)計(jì)十進(jìn)制加法電路，給出了基于并行前綴/進(jìn)位選擇結(jié)構(gòu)的條件推測性十進(jìn)制加法器的設(shè)計(jì)過程，并通過并行前綴單元對(duì)十進(jìn)制進(jìn)位選擇加法器進(jìn)行優(yōu)化設(shè)計(jì)。采用Verilog HDL對(duì)32 bit, 64 bit和128 bit十進(jìn)制加法器進(jìn)行描述并在ModelSim平臺(tái)上進(jìn)行了仿真驗(yàn)證，在Nangate Open Cell 45nm標(biāo)準(zhǔn)工藝庫下，通過Synopsys公司綜合工具Design Compiler進(jìn)行了綜合。與現(xiàn)有的條件推測性十進(jìn)制加法器相比較，綜合結(jié)果顯示該文所提出的十進(jìn)制加法器可以提升12.3%的速度性能。
    Abstract: There are increasing interests in hardware support for decimal arithmetic due to the demand of high accuracy computation in commercial computing, financial analysis, and other applications. New specifications for decimal floating-point arithmetic have been added to the revised IEEE 754-2008 standard. In this paper, the algorithm and architecture of decimal addition is studied comprehensively. A decimal adder is designed by using the parallel-prefix/carry-select architecture. The parallel-prefix unit is used to optimize the decimal carry select adder. The decimal adder has been realized by Verilog HDL and simulated with ModelSim. The synthesis results of this design by Design Compiler is also given and analyzed under Nangate Open Cell 45nm library. The results show that the delay performance of the proposed circuit can be improved by up to 12.3%.
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出版歷程
  • 收稿日期:  2015-12-14
  • 修回日期:  2016-06-08
  • 刊出日期:  2016-10-19

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