一種-100 dB電源抑制比的非帶隙基準(zhǔn)電壓源

黃國城; 尹韜; 朱淵明; 許曉冬; 張亞朝; 楊海鋼

doi:10.11999/JEIT151256

一種-100 dB電源抑制比的非帶隙基準(zhǔn)電壓源

doi: 10.11999/JEIT151256

2.
(中國科學(xué)院電子學(xué)研究所北京 100190) ②(中國科學(xué)院大學(xué) 北京 100190)

基金項(xiàng)目:

國家自然科學(xué)基金(61474120)，國家重點(diǎn)基礎(chǔ)研究發(fā)展計(jì)劃(2014CB744600)

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- 文章訪問數(shù): 2085
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出版歷程
- 收稿日期: 2015-11-09
- 修回日期: 2016-03-25
- 刊出日期: 2016-08-19

A -100 dB Power Supply Rejection Ratio Non-bandgap Voltage Reference

Funds:

The National Natural Science Foundation of China (61474120), The National Key Basic Research Program of China (2014CB744600)

摘要

摘要: 該文提出一種非帶隙基準(zhǔn)電路，通過一個(gè)帶超級源極跟隨器的預(yù)調(diào)制電路提供一個(gè)穩(wěn)定的電壓，為基準(zhǔn)核心電路供電。超級源極跟隨器通過降低基準(zhǔn)核心電路電源端的對地阻抗，有效提高了基準(zhǔn)電路的電源抑制能力。該基準(zhǔn)電路采用0.35 m CMOS 工藝設(shè)計(jì)并流片，測試結(jié)果表明，該電路的工作電源電壓為1.8~5 V，靜態(tài)電流約為13 A。低頻處電源抑制比(PSRR)約等于-100 dB，在小于1 kHz頻率范圍內(nèi)PSRR均優(yōu)于-93 dB。并且其片上面積僅為0.013 mm2。
- CMOS基準(zhǔn)電路 /
- 非帶隙基準(zhǔn)電路 /
- 預(yù)調(diào)制電路 /
- 超級源極跟隨器 /
- 電源抑制比
Abstract: This paper presents a non-bandgap voltage reference, which contains a pre-regulated circuit with a super source follower. The pre-regulated circuit includes a super source follower, which attenuates the impedance from the supply of the core reference circuit to ground. In this way, the pre-regulated circuit provides a relative stable voltage for the core reference circuit, improving the Power Supply Rejection Ratio (PSRR) of the output voltage of the reference. The proposed reference circuit is implemented in standard 0.35 m CMOS process. Measured results show that the supply range is from 1.8 to 5 V and the quiescent current is only about 13 A at room temperature. The PSRR at low frequency achieves -100 dB and the PSRR below 1 kHz is better than -93 dB. The active area of the proposed reference is only 0.013 mm2.
- CMOS reference circuit /
- Non-bandgap reference circuit /
- Pre-regulated circuit /
- Super source follower /
- Power Supply Rejection Ratio (PSRR)

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參考文獻(xiàn)(18)

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