一级黄色片免费播放|中国黄色视频播放片|日本三级a|可以直接考播黄片影视免费一级毛片

高級搜索

留言板

尊敬的讀者、作者、審稿人, 關(guān)于本刊的投稿、審稿、編輯和出版的任何問題, 您可以本頁添加留言。我們將盡快給您答復(fù)。謝謝您的支持!

姓名
郵箱
手機(jī)號碼
標(biāo)題
留言內(nèi)容
驗(yàn)證碼

基于四值脈沖參數(shù)模型的單粒子瞬態(tài)傳播機(jī)理與軟錯誤率分析方法

李悅 蔡剛 李天文 楊海鋼

李悅, 蔡剛, 李天文, 楊海鋼. 基于四值脈沖參數(shù)模型的單粒子瞬態(tài)傳播機(jī)理與軟錯誤率分析方法[J]. 電子與信息學(xué)報(bào), 2016, 38(8): 2113-2121. doi: 10.11999/JEIT151254
引用本文: 李悅, 蔡剛, 李天文, 楊海鋼. 基于四值脈沖參數(shù)模型的單粒子瞬態(tài)傳播機(jī)理與軟錯誤率分析方法[J]. 電子與信息學(xué)報(bào), 2016, 38(8): 2113-2121. doi: 10.11999/JEIT151254
LI Yue, CAI Gang, LI Tianwen, YANG Haigang. Propagation Mechanism of Single Event Transient and Soft Error Rate Analysis Method Based on Four-value Pulse Parameters Model[J]. Journal of Electronics & Information Technology, 2016, 38(8): 2113-2121. doi: 10.11999/JEIT151254
Citation: LI Yue, CAI Gang, LI Tianwen, YANG Haigang. Propagation Mechanism of Single Event Transient and Soft Error Rate Analysis Method Based on Four-value Pulse Parameters Model[J]. Journal of Electronics & Information Technology, 2016, 38(8): 2113-2121. doi: 10.11999/JEIT151254

基于四值脈沖參數(shù)模型的單粒子瞬態(tài)傳播機(jī)理與軟錯誤率分析方法

doi: 10.11999/JEIT151254
基金項(xiàng)目: 

國家自然科學(xué)基金(61271149),國家科技重大專項(xiàng)資助(2013ZX03006004)

Propagation Mechanism of Single Event Transient and Soft Error Rate Analysis Method Based on Four-value Pulse Parameters Model

Funds: 

The National Natural Science Foundation of China (61271149), The National Science and Technology Major Special Fund (2013ZX03006004)

  • 摘要: 隨著工藝尺寸的不斷縮小,由單粒子瞬態(tài)(Single Event Transient, SET)效應(yīng)引起的軟錯誤已經(jīng)成為影響宇航用深亞微米VLSI電路可靠性的主要威脅,而SET脈沖的產(chǎn)生和傳播也成為電路軟錯誤研究的熱點(diǎn)問題。通過研究SET脈沖在邏輯鏈路中的傳播發(fā)現(xiàn):脈沖上升時間和下降時間的差異能夠引起輸出脈沖寬度的展寬或衰減;脈沖的寬度和幅度可決定其是否會被門的電氣效應(yīng)所屏蔽。該文提出一種四值脈沖參數(shù)模型可準(zhǔn)確模擬SET脈沖形狀,并采用結(jié)合查找表和經(jīng)驗(yàn)公式的方法來模擬SET脈沖在電路中的傳播過程。該文提出的四值脈沖參數(shù)模型可模擬SET脈沖在傳播過程中的展寬和衰減效應(yīng),與單參數(shù)脈沖模型相比計(jì)算精度提高了2.4%。該文應(yīng)用基于圖的故障傳播概率算法模擬SET脈沖傳播過程中的邏輯屏蔽,可快速計(jì)算電路的軟錯誤率。對ISCAS89及ISCAS85電路進(jìn)行分析的實(shí)驗(yàn)結(jié)果表明:該方法與HSPICE仿真方法的平均偏差為4.12%,計(jì)算速度提升10000倍。該文方法可對大規(guī)模集成電路的軟錯誤率進(jìn)行快速分析。
  • 王真, 李舫, 盧芳芳. 電路軟差錯率評估綜述[J]. 上海電力學(xué)院學(xué)報(bào), 2015, 31(4): 369-375. doi: 10.3969/j.issn.1006-4729. 2015.04.013.
    WANG Zhen, LI Fang, and LU Fangfang. Survey on circuit soft error rate evaluation[J]. Journal of Shanghai University of Electric Power, 2015, 31(4): 369-375. doi: 10.3969/j.issn. 1006-4729.2015.04.013.
    閆愛斌, 梁華國, 黃正峰, 等. 基于故障概率的組合電路軟錯誤率分析[J]. 電子測量與儀器學(xué)報(bào), 2015, 29(3): 343-351. doi: 10.13382/j.jemi.2015.03.005.
    YAN Aibin, LIANG Huaguo, HUANG Zhengfeng, et al. Fault probability based SER analysis for combinational logic circuits[J]. Journal of Electronic Measurement and Instrumentation, 2015, 29(3): 343-351. doi: 10.13382/j.jemi. 2015.03.005.
    HENKEL J, BAUER L, DUTT N, et al. Reliable on-chip systems in the nano-era: Lessons learnt and future trends[C]. 50th ACM/EDAC/IEEE Design Automation Conference, Austin, TX, USA, 2013: 1-10. doi: 10.1145/2463209.2488857.
    徐東超, 繩偉光, 何衛(wèi)鋒. 面向SystemC的軟錯誤敏感度分析方法[J]. 微電子學(xué)與計(jì)算機(jī), 2015, 32(9): 60-64.
    XU Dongchao, SHENG Weiguang, and HE Weifeng. Method to analyze soft error sensitivity for SystemC[J]. Microelectronics Computer, 2015, 32(9): 60-64.
    蔡爍, 鄺繼順, 張亮, 等. 基于差錯傳播概率矩陣的時序電路軟錯誤可靠性評估[J]. 計(jì)算機(jī)學(xué)報(bào), 2015, 38(5): 923-931. doi: 10.3724/SP.J.1016.2015.00923.
    CAI Shuo, KUANG Jishun, ZHANG Liang, et al. Reliability estimation for soft error of sequential circuit based on error propagation probability matrix[J]. Chinese Journal of Computer, 2015, 38(5): 923-931. doi: 10.3724/SP.J.1016. 2015.00923.
    MAHATME N N, GASPARD N J, ASSIS T, et al. Impact of technology scaling on the combinational logic soft error rate[C]. IEEE International Reliability Physics Symposium, Waikoloa, HI, USA, 2014: 5F.2.1-5F.2.6. doi: 10.1109/IRPS. 2014. 6861093.
    MOHANRAM K. Simulation of transients caused by single- event upsets in combinational logic[C]. IEEE International Test Conference, Austin, TX, USA, 2005: 973-981. doi: 10.1109/TEST. 2005.1584063.
    WANG F, XIE Y, RAJARAMANT R, et al. Soft error rate analysis for combinational logic using an accurate electrical masking model[C]. 20th International Conference on VLSI Design, Bangalore, India, 2007: 165-170. doi: 10.1109/ VLSID.2007. 145.
    MANSOUR W and VELAZCO R. An automated SEU fault-injection method and tool for HDL-based designs[J]. IEEE Transactions on Nuclear Science, 2013, 60(4): 2728-2733. doi: 10.1109/TNS.2013.2267097.
    ENTRENA L, VALDERAS M G, CARDENAL R F, et al. Soft error sensitivity evaluation of mi-croprocessors by multilevel emulation-based fault injection[J]. IEEE Transactions on Computers, 2012, 61(3): 313-322. doi: 10.1109/TC.2010.262.
    ZHANG Ming and SHANBHAG N R. Soft-error-rate- analysis (SERA) methodology[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(10): 2140-2155. doi: 10.1109/ICCAD.2004.1382553.
    RAJARAMANT R, KIM J S, VIJAYKRISHNAN N, et al. SEAT-LA: a soft error analysis tool for combinational logic[C]. Proceedings of the 19th International Conference on VLSI Design, Hyderabad, India, 2006: 499-502. doi: 10.1109/ VLSID.2006.143.
    RAO R R, CHOPRA K, BLAAUW D T, et al. Computing the soft error rate of a combinational logic circuit using parameterized descriptors[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007, 26(3): 468-479. doi: 10.1109/TCAD.2007.891036.
    ZIVANOV N M and MARCULESCU D. Circuit reliability analysis using symbolic techniques[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(12): 2638-2649. doi: 10.1109/TCAD.2006.882592.
    ZIVANOV N M and MARCULESCU D. Modeling and optimization for soft-error reliability of sequential circuits[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(5): 803-816. doi: 10.1109/ TCAD.2008.917591.
    ASADI H, TAHOORI M B, FAZELI M, et al. Efficient algorithms to accurately compute derating factors of digital circuits[J]. Microelectronics Reliability, 2012, 52: 1215-1226.
    HAMAD G, HASAN S, MOHAMED O, et al. New insights into the single event transient propagation through static and TSPC logic[J]. IEEE Transactions on Nuclear Science, 2014, 61(4): 1618-1627. doi: 10.1109/TNS.2014.2305434.
    ARTOLA L, GAILLARDIN M, HUBERT G, et al. Modeling single event transients in advanced devices and ICs[J]. IEEE Transactions on Nuclear Science, 2015, 62(4): 1528-1539. doi: 10.1109/TNS.2015.2432271.
    SHIVAKUMAR P, KISTLER M, KECKLER S W, et al. Modeling the effect of technology trends on the soft error rate of combinational logic[C]. International Conference on Dependable Systems and Networks, Bethesda, MD, USA, 2002: 389-398. doi: 10.1109/DSN.2002.1028924.
    OMANA M, PAPASSO G, ROSSI D, et al. A model for transient fault propagation in combinational logic[C]. Proceedings of the 9th IEEE International On-Line Testing Symposium, Greece, 2003: 111-115. doi: 10.1109/ICECS. 2015.7440265.
    FIROUZI F, KIAMEHR S, MONSHIZADEH P, et al. A model for transient fault propagation considering glitch amplitude and rise-fall time mismatch[C]. 2nd Asia Symposium on Quality Electronic Design, Penang, Malaysia, 2010: 89-92. doi: 10.1109/ASQED.2010.5548223.
    RAO R R, CHOPRA K, BLAAUW D, et al. An efficient static algorithm for computing the soft error rates of combinational circuits[C]. Design, Automation and Test in Europe, Munich, Germany, 2006, 1: 1-6. doi: 10.1109/DATE. 2006. 244060.
    ZHANG B, WANG W S, and ORSHANSKY M. FASER: fast analysis of soft error susceptibility for cell-based designs[C]. Proceedings of the 7th International Symposium on Quality Electronic Design, San Jose, CA, USA, 2006: 755-760. doi: 10.1109/ISQED.2006.64.
  • 加載中
計(jì)量
  • 文章訪問數(shù):  1241
  • HTML全文瀏覽量:  153
  • PDF下載量:  426
  • 被引次數(shù): 0
出版歷程
  • 收稿日期:  2015-11-09
  • 修回日期:  2016-04-01
  • 刊出日期:  2016-08-19

目錄

    /

    返回文章
    返回