面向DVB-S2標(biāo)準(zhǔn)LDPC碼的高效編碼結(jié)構(gòu)
doi: 10.11999/JEIT151198
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2.
(中國科學(xué)院電子學(xué)研究所可編程芯片與系統(tǒng)研究室 北京 100190) ②(中國科學(xué)院大學(xué) 北京 100049)
基金項(xiàng)目:
國家自然科學(xué)基金(61404140, 61271149, 61106033)
Efficient Encoding Architecture for LDPC Code Based on DVB-S2 Standard
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2.
(System of Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)
Funds:
The National Natural Science Foundation of China (61404140, 61271149, 61106033)
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摘要: 面向DVB-S2標(biāo)準(zhǔn)LDPC碼，該文旨在實(shí)現(xiàn)一種基于FPGA的高效編碼結(jié)構(gòu)，提出一種快速流水線并向遞歸編碼算法，可以顯著提高編碼數(shù)據(jù)信息吞吐率。同時(shí)，通過并向移位運(yùn)算和并向異或運(yùn)算的處理結(jié)構(gòu)計(jì)算編碼中間變量及校驗(yàn)位信息，在提高編碼并行度的同時(shí)可有效減少存儲(chǔ)資源的消耗。此外，針對(duì)動(dòng)態(tài)自適應(yīng)編碼的情況優(yōu)化了LDPC碼編碼存儲(chǔ)結(jié)構(gòu)，有效復(fù)用了數(shù)據(jù)存儲(chǔ)單元和RAM地址發(fā)生器，進(jìn)一步提高FPGA的硬件邏輯資源利用率。針對(duì)DVB-S2標(biāo)準(zhǔn)LDPC碼，基于Stratix IV系列FPGA的驗(yàn)證結(jié)果表明，所提編碼結(jié)構(gòu)在系統(tǒng)時(shí)鐘為126.17 MHz時(shí)，編碼數(shù)據(jù)信息吞吐率達(dá)20 Gbps以上。
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關(guān)鍵詞:
- LDPC碼 /
- 編碼結(jié)構(gòu) /
- DVB-S2標(biāo)準(zhǔn) /
- FPGA
Abstract: For DVB-S2 standard LDPC code, to achieve an efficient encoding architecture based on FPGA, a fast pipeline parallel and recursive encoding algorithm is proposed which can significantly improve encoding speed and improve the encoding data rate of information throughput. At the same time, the parallel shift operation and parallel XOR processing structure is introduced to calculate code intermediate variable. It can effectively improve the encoding parallel degree and reduce the occupancy volume of storage resources. In addition, according to dynamic adaptive encoding, the storage structure and effective reuse of data storage unit and the RAM address generator are optimized. In this case, the utilization of FPGA resources is further improved. The experiment based on Stratix IV series FPGA for DVB-S2 standard LDPC code, shows that the proposed method can achieve system clock frequency of 126.17 MHz and encoding data rate of information throughput of more than 20 Gbps.-
Key words:
- LDPC code /
- Encoding architecture /
- DVB-S2 standard /
- FPGA
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