一種用于測試數(shù)據(jù)壓縮的自適應(yīng)EFDR編碼方法
doi: 10.11999/JEIT150177
基金項目:
國家自然科學(xué)基金(61472123, 60673085)
Adaptive EFDR Coding Method for Test Data Compression
Funds:
The National Natural Science Foundation of China (61472123, 60673085)
-
摘要: 該文提出一種用于測試數(shù)據(jù)壓縮的自適應(yīng)EFDR(Extended Frequency-Directed Run-length)編碼方法。該方法以EFDR編碼為基礎(chǔ),增加了一個用于表示后綴與前綴編碼長度差值的參數(shù)N,對測試集中的每個測試向量,根據(jù)其游程分布情況,選擇最合適的N值進(jìn)行編碼,提高了編碼效率。在解碼方面,編碼后的碼字經(jīng)過簡單的數(shù)學(xué)運算即可恢復(fù)得到原測試數(shù)據(jù)的游程長度,且不同N值下的編碼碼字均可使用相同的解碼電路來解碼,因此解碼電路具有較小的硬件開銷。對ISCAS-89部分標(biāo)準(zhǔn)電路的實驗結(jié)果表明,該方法的平均壓縮率達(dá)到69.87%,較原EFDR編碼方法提高了4.07%。
-
關(guān)鍵詞:
- 測試數(shù)據(jù)壓縮 /
- EFDR(Extended Frequency-Directed Run-length)編碼 /
- 自適應(yīng)EFDR編碼 /
- 解碼
Abstract: An adaptive Extended Frequency-Directed Run-length (EFDR) code method for test data compression is presented in this paper. The method is based on EFDR code, and adds an additional parameter N, which is used to represent the code length difference between tail and prefix. According to the distribution of the runs in each test vector of the test set, the method selects the most suitable N values to code, and it can improve the compression ratio. For the decompression, according to the size of the codeword, the run length of the original test data can be obtained with a simple mathematical operation. Meanwhile, those codeword under different parameter values can be decoded by the same decompression circuit. Thus, the decompression circuit can keep in a low hardware cost level. The experimental result shows that the average compression rate of the proposed method can achieve to 69.87%, over 4.07% than original EFDR code method. -
Mehta U S, Dasgupta K S, and Evashrayee N J. Un-length-based test data compression techniques: how far from entropy and power bounds a survey[J]. VLSI Design, 2010(1): 1-9. 劉鐵橋, 鄺繼順, 蔡爍. 一種將測試集嵌入到Test-per-Clock位流中的方法[J]. 計算機研究與發(fā)展, 2014, 51(9): 2022-2029. Liu Tie-qiao, Kuang Ji-shun, and Cai Shuo. A new method of embedding test patterns into test-per-clock bit stream[J]. Journal of Computer Research and Development, 2014, 51(9): 2022-2029. Anshuman C and Krishnendu C. Frequency-Directed Run- length(FDR) codes with application to system-on-a-chip test data compression[C]. Proceedings of the 19th IEEE VLSI Test Symposium, Atlantic, 2001: 42-47. EL-Maleh A H. Test data compression for system-on-a-chip using Extended Frequency-Directed Run-Length Code[J]. IET Computers Digital Techniques, 2008(2): 155-163. Dauh T W and Jen L L. Test data compression using multi-dimensional pattern run-length codes[J]. Journal Electron Test, 2010, 26(3): 393-400. Ye B, Zhao Q, Zhou D, et al.. Test data compression using alternating variable run-length code[J]. INTEGRATION, the VLSI Journal, 2011(44): 103-110. 梁華國, 蔣翠云, 羅強. 應(yīng)用對稱編碼的測試數(shù)據(jù)壓縮方法[J]. 計算機研究與發(fā)展, 2011, 48(12): 2391-2399. Liang Hua-guo, Jiang Cui-yun, and Luo Qiang. Test data compression and decompression using symmetry-variable codes[J]. Journal of Computer Research and Development, 2011, 48(12): 2391-2399. 馬會, 鄺繼順, 馬偉. 基于一位標(biāo)識的測試向量混合編碼壓縮方法[J]. 電子測量與儀器學(xué)報, 2013, 27(4): 312-318. Ma Hui, Kuang Ji-shun, and Ma Wei. Hybrid coding compression method of test vector based on an identification [J]. Journal of Electronic Measurement and Instrument, 2013, 27(4): 312-318. Gonciari P T, AI-Hashimi B M, and Nicolici N. Variable- length input Huffman coding for system-on-a-chip test[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003, 22(6): 783-789. EL-Maleh A H. Efficient test compression technique based on block merging[J]. IET Computer Digital Techniques, 2008, 5(2): 327-335. Zhang L and Kuang J S. Test data compression using selective sparse storage[J]. Journal Electron Test, 2011, 27(4): 565-577. 劉杰, 易茂祥, 朱勇. 采用字典詞條衍生模式的測試數(shù)據(jù)壓縮[J]. 電子與信息學(xué)報, 2012, 34(1): 231-235. Liu Jie, Yi Mao-xiang, and Zhu Yong. Test data compression using entry derivative mode of dictionary[J]. Journal of Electronics Information Technology, 2012, 34(1): 231-235. Sismanoglou P and Nikolos D. Test data compression based on reuse and bit-flipping of parts of dictionary entries[C]. Proceedings of 17th International Symposium on Design and Diagnostics of Electronic Circuits Systems, Warsaw, 2014: 110-115. Tyszer J, Filipek M, Mrugalski G, et al.. New test compression scheme based on low power BIST[C]. Processdings of 18th IEEE European Test Symposium, Avignon, 2013: 1-6. Chloupek M, Jenicek J, Novak O, et al.. Test pattern decompression in parallel scan chain architecture[C]. Proceedings of 16th International Symposium on Design and Diagnostics of Electronic Circuits Systems, Karlovy, 2013: 219-223. 方昊, 姚博, 宋曉笛. 雙游程編碼的無關(guān)位填充算法[J]. 電子學(xué)報, 2009, 37(1): 1-7. Fang Hao, Yao Bo, and Song Xiao-di. The algorithm of filling X bits in dual-run-length coding[J]. Acta Electronica Sinica, 2009, 37(1): 1-7. -
計量
- 文章訪問數(shù): 1246
- HTML全文瀏覽量: 140
- PDF下載量: 449
- 被引次數(shù): 0