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一種用于加速FPGA設(shè)計空間探索的電路特性驅(qū)動半監(jiān)督建模方法

楊立群,  李威,  黃志洪,  孫嘉斌,  楊海鋼

楊立群, 李威, 黃志洪, 孫嘉斌, 楊海鋼. 一種用于加速FPGA設(shè)計空間探索的電路特性驅(qū)動半監(jiān)督建模方法[J]. 電子與信息學報, 2015, 37(10): 2521-2528. doi: 10.11999/JEIT150162
引用本文: 楊立群, 李威, 黃志洪, 孫嘉斌, 楊海鋼. 一種用于加速FPGA設(shè)計空間探索的電路特性驅(qū)動半監(jiān)督建模方法[J]. 電子與信息學報, 2015, 37(10): 2521-2528. doi: 10.11999/JEIT150162
Yang Li-qun, Li Wei, Huang Zhi-hong, Sun Jia-bin, Yang Hai-gang. Circuit Characteristics-driven Semi-supervised Modelling Approach for Accelerating FPGA Design Space Exploration[J]. Journal of Electronics & Information Technology, 2015, 37(10): 2521-2528. doi: 10.11999/JEIT150162
Citation: Yang Li-qun, Li Wei, Huang Zhi-hong, Sun Jia-bin, Yang Hai-gang. Circuit Characteristics-driven Semi-supervised Modelling Approach for Accelerating FPGA Design Space Exploration[J]. Journal of Electronics & Information Technology, 2015, 37(10): 2521-2528. doi: 10.11999/JEIT150162

一種用于加速FPGA設(shè)計空間探索的電路特性驅(qū)動半監(jiān)督建模方法

doi: 10.11999/JEIT150162
  • 2.

    (中國科學院電子學研究所 北京 100190) ②(中國科學院大學 北京 100049)

基金項目: 

國家自然科學基金(61271149)

Circuit Characteristics-driven Semi-supervised Modelling Approach for Accelerating FPGA Design Space Exploration

  • 2.

    (Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)

Funds: 

The National Natural Science Foundation of China (61271149)

  • 摘要: 該文提出一種電路特性驅(qū)動的半監(jiān)督建模方法來探索FPGA架構(gòu)設(shè)計空間。通過加入電路特性作為輸入來構(gòu)建一個通用的FPGA性能模型，該方法能夠精確預(yù)測指定電路在特定FPGA架構(gòu)上實現(xiàn)的性能。實驗結(jié)果顯示該方法在預(yù)測電路在FPGA上實現(xiàn)的面積時，平均相對誤差達到6.25%；預(yù)測延時時，平均相對誤差可達4.23%，具有與半監(jiān)督模型樹(Semi-supervised Model Tree, SMT)方法可比的預(yù)測精度。同時，該文方法加速了FPGA性能建模過程，與SMT方法比較，在6核Intel服務(wù)器平臺Intel Xeon E7-4807上，探索具有百萬架構(gòu)的FPGA設(shè)計空間時，該文方法可將時間成本由500 h降低為250 h。
    Abstract: A circuit characteristics-driven semi-supervised modelling approach is proposed for FPGA architecture design space exploration. By including circuit characteristics as input, the proposed approach can estimate the performance of specific circuit on certain architecture accurately. Experimental results illustrate that the approach estimates the area with Mean Relative Error (MRE) up to 6.25%, and delay up to 4.23%, which is comparable to the Semi-supervised Model Tree (SMT) approach. Meanwhile, the proposed approach speedups the modelling process. Compared to the SMT approach, the proposed approach reduces the time cost from 500 h to 250 h when exploring a design space with millions of architectures inside on Intel Xeon E7-4807 platform.
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出版歷程
  • 收稿日期:  2015-01-28
  • 修回日期:  2015-04-22
  • 刊出日期:  2015-10-19

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