動態(tài)自適應(yīng)低密度奇偶校驗碼譯碼器的FPGA實(shí)現(xiàn)
doi: 10.11999/JEIT141609
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2.
(中國科學(xué)院電子學(xué)研究所可編程芯片與系統(tǒng)研究室 北京 100190) ②(中國科學(xué)院大學(xué) 北京 100086)
基金項目:
國家自然科學(xué)基金(61404140, 61271149, 61106033)
Design of Dynamic Adaptive LDPC Decoder Based on FPGA
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2.
(System on Programmable Chip Research Department, Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)
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摘要: 在復(fù)雜深空通信環(huán)境中，自適應(yīng)能力的強(qiáng)弱對低密度奇偶校驗(LDPC)碼譯碼器能否保持長期穩(wěn)定工作具有重要影響。該文通過對DVB-S2標(biāo)準(zhǔn)LDPC碼譯碼器各功能模塊的IP化設(shè)計，將動態(tài)自適應(yīng)理論參數(shù)化映射到各功能模塊中，實(shí)現(xiàn)動態(tài)自適應(yīng)LDPC碼譯碼器的設(shè)計。基于Stratix IV系列FPGA的驗證結(jié)果表明，動態(tài)自適應(yīng)LDPC譯碼器可以滿足不同碼率碼長及不同性能需求下的譯碼。同時，單譯碼通道可以保證譯碼數(shù)據(jù)信息吞吐率達(dá)到40.9~71.7 Mbps。
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關(guān)鍵詞:
- LDPC碼譯碼器 /
- 動態(tài)自適應(yīng) /
- DVB-S2標(biāo)準(zhǔn) /
- FPGA
Abstract: Faced with the complex environment of deep space communication, the adaptive capacity can have an impact on the ability of the Low Density Parity Check (LDPC) code decoder to maintain long-term stability. This paper proposes a design method of dynamic adaptive LDPC code decoder. Through the IP-based design of each function module, the design method of dynamic adaptive can be mapped to each function module in DVB-S2 LDPC code decoder. The verification results based on the Stratix IV FPGA show the dynamic adaptive LDPC code decoder not only can decode under the different code length and code rate, but also can decode under the different decoding performance. Meanwhile, the single-channel decoder can ensure the information throughput to reach to 40.9~71.7 Mbps.-
Key words:
- Low Density Parity Check (LDPC) code decoder /
- Dynamic adaptive /
- DVB-S2 standard /
- FPGA
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