一種考慮空間關(guān)聯(lián)工藝偏差的統(tǒng)計靜態(tài)時序分析方法
doi: 10.11999/JEIT140295
基金項目:
國家科技重大專項(2013ZX03006004)和國家自然科學基金(61106033)資助課題
A Statistical Static Timing Analysis Incorporating Process Variations with Spatial Correlations
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摘要: 為了準確評估工藝參數(shù)偏差對電路延時的影響，該文提出一種考慮空間關(guān)聯(lián)工藝偏差的統(tǒng)計靜態(tài)時序分析方法。該方法采用一種考慮非高斯分布工藝參數(shù)的二階延時模型，通過引入臨時變量，將2維非線性模型降階為1維線性模型；再通過計算到達時間的緊密度概率、均值、二階矩、方差及敏感度系數(shù)，完成了非線性非高斯延時表達式的求和、求極大值操作。經(jīng)ISCAS89電路集測試表明，與蒙特卡洛仿真(MC)相比，該方法對應延時分布的均值、標準差、5%延時點及95%延時點的平均相對誤差分別為0.81%, -0.72%, 2.23%及-0.05%，而運行時間僅為蒙特卡洛仿真的0.21%，證明該方法具有較高的準確度和較快的運行速度。
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關(guān)鍵詞:
- 集成電路 /
- 統(tǒng)計靜態(tài)時序分析 /
- 空間關(guān)聯(lián) /
- 非高斯非線性 /
- 工藝偏差 /
- 延時模型
Abstract: To evaluate effects of process variations on circuit delay accurately, this study proposes a Statistical Static Timing Analysis (SSTA) which incorporates process variations with spatial correlations. The algorithm applies a second order delay model that taking into account the non-Gaussian parameters - by inducting the notion of conditional variables, the 2D non-linear delay model is translated into 1D linear one; and by computing the tightness probability, mean, variance, second-order moment and sensitivity coefficients of the circuit arrival time, the sum and max operations of non-linear and non-Gaussian delay expressions are implemented. For the ISCAS89 benchmark circuits, as compared to Monte Carlo (MC) simulation, the average errors of 0.81%, -0.72%, 2.23% and -0.05%, in the mean, variance, 5% and 95% quantile points of the circuit delay are obtained respectively for the proposed method. The runtime of the proposed method is about 0.21% of the value of Monte Carlo simulation. The experimental results prove that the high accuracy of the SSTA is reliable. -
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