低功耗Clock-Gating技術(shù)在SAR實(shí)時(shí)成像處理中的應(yīng)用
Low Power Clock-Gating Method and Its Applications in SAR Real-Time Processor
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摘要: 功耗問(wèn)題在SAR實(shí)時(shí)成像系統(tǒng)中是不容忽視的。該文以實(shí)時(shí)成像系統(tǒng)中的輸入分機(jī)為研究平臺(tái),測(cè)試了信號(hào)處理中常用芯片DSP,SBSRM,FPGA在采用Clock-gating技術(shù)前后,功耗的變化。通過(guò)大量的實(shí)驗(yàn)結(jié)果,驗(yàn)證了Clock-gating技術(shù)在SAR實(shí)時(shí)信號(hào)處理中的可行性,對(duì)降低SAR實(shí)時(shí)成像系統(tǒng),尤其是星載實(shí)時(shí)成像系統(tǒng)的功耗有一定的指導(dǎo)意義。Abstract: Power consumption has to be taken into consideration in an applied SAR real-time processor. The power consumption is measured before and after clock-gating method had been applied to DSP, SBSRAM and FPGA of an air-borne SAR real-time preprocessor board respectively by software. It has been proved that clock-gating method is feasible for low power design in the SAR especially the future space-borne SAR real-time processor.
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