等平面化自對準(zhǔn)硅雪崩擊穿電子發(fā)射陣列器件的設(shè)計(jì)和研究
DESIGN AND RESEARCH OF QUASI-PLANAR SELF-ALIGNED SILICON AVALANCHE ELECTRON EMISSION ARRAY
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摘要: 本文報(bào)道了等平面化自對準(zhǔn)硅雪崩擊穿電子發(fā)射陣列器件的結(jié)構(gòu)設(shè)計(jì)和工藝過程。該器件的電子發(fā)射區(qū)域邊緣的工藝臺階僅為10nm,其自對準(zhǔn)的淺砷注入電流通道區(qū)寬度僅為3m。與已報(bào)道的其它結(jié)構(gòu)硅雪崩擊穿電子發(fā)射器件相比較,該器件的電流電壓特性曲線有更寬的線性區(qū)域和更低的通導(dǎo)電阻。本文也對其電子發(fā)射特性作了部分介紹。
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關(guān)鍵詞:
- 真空微電子學(xué); 電子發(fā)射; 冷陰極
Abstract: The device structure and technical processings of quasi-planar self-aligned silicon avalanche electron emission array are introduced. The processing step at the edge of electron emission region is about 100 nm only and the width of self-aligned current channel of shallow As implantation is about 3 m. Its I-V characteristics show a larger linear region and lower series resistance than that of the previous silicon avalanche electron emission devices. Some of the electron emission characteristics are also discussed in the paper. -
黃慶安.真空微電子學(xué)的研究與進(jìn)展.電子學(xué)報(bào),1995, 23(10): 134-138.[2]Yicheng Lu, Minjng Wang, Bogoljub Lalevic. IEEE Trans. on ED, 1994, ED-41(3): 439-444.[3]Wang M, Lu Y, Lalevic B. J. Vac. Sci. Technol, 1993, B-11(2): 426-428[4]Meijuan Guo. Proc. 4th Int. Con. on Solid-State and Integrated Circuit Technology.北京:電子工業(yè)出版社,1995,485-487.[5]S M Sze. VLSI Technology. 2nd Ed, McGraw-Mill, 1988, ch.3: 111-113. -
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