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可重構結構設計空間快速搜索方法

季愛明 沈海斌 嚴曉浪

季愛明, 沈海斌, 嚴曉浪. 可重構結構設計空間快速搜索方法[J]. 電子與信息學報, 2006, 28(9): 1744-1747.
引用本文: 季愛明, 沈海斌, 嚴曉浪. 可重構結構設計空間快速搜索方法[J]. 電子與信息學報, 2006, 28(9): 1744-1747.
Ji Ai-ming, Shen Hai-bin, Yan Xiao-lang. A Fast Method for Reconfigurable Architecture Design Space Exploration[J]. Journal of Electronics & Information Technology, 2006, 28(9): 1744-1747.
Citation: Ji Ai-ming, Shen Hai-bin, Yan Xiao-lang. A Fast Method for Reconfigurable Architecture Design Space Exploration[J]. Journal of Electronics & Information Technology, 2006, 28(9): 1744-1747.

可重構結構設計空間快速搜索方法

A Fast Method for Reconfigurable Architecture Design Space Exploration

  • 摘要: 在可重構結構評估模型的基礎上,研究了在算法級估計可重構結構的面積、性能和功耗的方法。根據(jù)面積、性能和功耗,分兩步搜索可重構結構的設計空間。首先,搜索結構域中每個結構實現(xiàn)所有算法時的最小代價,其次,在結構設計空間中搜索最優(yōu)結構。該方法不依賴任何具體的架構,全面評價可重構結構的優(yōu)劣,能快速獲得全局最優(yōu)的搜索結果。應用實例表明,在可重構結構設計初期,該方法能有效地指導可重構結構的設計。
  • Rose J A, El Gamal A, Sangiovannt-Vincenteli A. Architecture of field programmable gate arrays[J].Proc. IEEE.1993, 81(7):1013-1029[2]Hartenstein R, Hofmann T H, Nageldinger U. Design-space exploration of low power coarse grained reconfigurable datapath array architectures. Proc. of Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop. Gottingen, Germany, 2000: 118-128.[3]Hartenstein R. A decade of reconfigurable computing: a visionary retrospective. Proceedings of Conference on Design, Automation and Test in Europe. Munich, Germany, 2001: 642- 649.[4]Hartenstein R , Herz M , Hofmann T, et al.. KressArray Xplorer:a new CAD environment to optimize reconfigurable datapath array architectures. Proceedings of the ASP-DAC 2000, Yokohama , Japan, 2000: 163-168.[5]Betz V, Rose J, Marquart A. Architecture and CAD for Deep Submicron FPGAs. Dordrecht: Kluwer Academic Publishers, 1999: 50-61.[6]Bossuet L, Gogniat G, Philippe J L. Fast design spaceexploration method for reconfigurable architectures. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, CSREA, 2003.[7]Darnauer J, Dai W W. A method for generation random circuits and its application to routability measurement. Proc of International Conference on Symp. Field Programmable Gate Arrays, 1996: 66-72.[8]Davis J A, De V K, Meundl J D. A stochastic wire-length distribution for GigaScale Integration (GSI)Part I: Derivation and validation[J].IEEE Trans. on Electron Devices.1998, 45(3):580-589[9]Kahng A B, Mantik S, Stroobandt D. Toward accurate models of achievable routing[J].IEEE Trans. on Computer Aided Design of Intergrated Circuits and System.2001, 20(5):648-658[10]Bossuet L .[J].Wayne B , Guy G, et al.. Targeting tiled architectures in design exploration. Proc of the International Parallel and Distributed Processing Symposium (IPDPS03). Austin : IEEE Computer Society.2003,:-[11]Landman P. High-level power estimation. Low Power Electronics and Design, 1996., International Symposium on Monterey CA, 1996:29-35.
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出版歷程
  • 收稿日期:  2004-12-31
  • 修回日期:  2005-08-08
  • 刊出日期:  2006-09-19

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