集成電路參數(shù)中心值和容差的耦合設計方法
The Coupling Technique for ICs Centering Design and Tolerance Optimization
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摘要: 基于對集成電路參數(shù)成品率中心值設計和容差分配的研究,該文提出了一種參數(shù)成品率中心值設計和容差分配耦合求解最優(yōu)設計值的算法。該算法不需要設計者對電路或工藝的物理結(jié)構(gòu)非常熟悉,從任意初始設計值和任意大小的容差,算法均可收斂到可接受域中的最優(yōu)設計值。另外,根據(jù)工藝線的容差,算法可確定集成電路的最優(yōu)參數(shù)成品率,也可根據(jù)實際要求選擇適當容差的工藝線,以降低生產(chǎn)成本、提高效益。最后用實例證明了該算法的可行性和實用性,得到了滿意的結(jié)果。Abstract: A coupling technique is proposed based on parametric yields centering design and tolerance optimization. The technique is convergence to the optimal normal values from given initial design variable and tolerance with little knowledge of circuit, device or technology. In the optimal value, the maximum yield can be obtained according to technology condition while proper technology conditions can be chosen according to practical requirements. Finally, the feasibility and utility of the method are demonstrated satisfactorily by numerical and practical examples.
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Soin R S, Spence R. Statistical exploration approach to design centering. IEE Proc. -G, 1980, 127(6): 260- 269.[2]郝躍.集成電路制造動力學理論與方法.高科技教育叢書,北京:教育出版社等聯(lián)合出版,1995:284-291.[3]Say Wei Foo, Yu Lin. Hybrid method of tolerance design[J].Proceedings of ICECS99, The 6th IEEE International Conference on Electronics, Circuits and Systems.1999, 1:557-[4]Bandler J W. Optimization of design tolerance using nonlinear programming[J].Journal of optimization and application.1974,14(1):99-[5]凌燮亭.電路參數(shù)的容差分析與設計.上海:復旦大學出版社,1991:100-177.[6]甘學溫,杜剛,肖志光.實驗設計與模擬相結(jié)合用于IC優(yōu)化設計的TCAD工具.北京大學學報(自然科學版),2002,38(5):713-717.[7]魯勇,張文俊,楊之廉.響應表面法在工藝綜合中的應用.半導體學報,2002,23(10):1106-1120.[8]Abdel-Malek H L, Hassan A-K S O. The ellipsoidal technique for design centering and region approximation. IEEE Trans. on CAD/AC, 1991, 11(8): 1006- 1014. -
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