基于時(shí)間約束的FPGA數(shù)字水印

陸健峰; 王朔中

基于時(shí)間約束的FPGA數(shù)字水印

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出版歷程
- 收稿日期: 2003-06-28
- 修回日期: 2003-10-20
- 刊出日期: 2004-12-19

FPGA Watermarking Based on Modification of Time Constraints

摘要

摘要: 該文提出一種基于時(shí)間約束的FPGA數(shù)字水印技術(shù),其基本思想是將準(zhǔn)備好的水印標(biāo)記嵌入非關(guān)鍵路徑上的時(shí)間約束來(lái)定制最終的下載比特流文件,同時(shí)并不改變?cè)O(shè)計(jì)的原始性能.這一方法能保證水印標(biāo)記所對(duì)應(yīng)的下載比特流文件的唯一性,從而可對(duì)FPGA設(shè)計(jì)模塊的所有權(quán)提供強(qiáng)有力的證明。與其他方法相比,該文提出的技術(shù)不僅具有零空間開銷和低時(shí)間開銷,而且還有效地提高了信息嵌入量。
- 知識(shí)產(chǎn)權(quán); 數(shù)字水印; 現(xiàn)場(chǎng)可編程門陣列; 時(shí)間約束
Abstract: Based on modification of time constraints in the FPGA design, a watermark-embedding scheme is proposed for protection of intellectual property rights of the system designer. A coded binary watermark sequence is used to replace the least significant digits of the time constraints in some non-critical paths. The modified time constraints lead to substantial and unique changes in the generated bit stream without altering the performance of the design, both in terms of space and time overheads and the system functionality. The embedded data can be extracted in a reverse procedure. The paper provides a scheme with zero area and low timing overheads, and a significant increase in embedding capacity in comparison with some existing techniques.

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參考文獻(xiàn)(1)

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