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高性能半靜態(tài)雙邊沿D觸發(fā)器

王倫耀 夏銀水 葉錫恩

王倫耀, 夏銀水, 葉錫恩. 高性能半靜態(tài)雙邊沿D觸發(fā)器[J]. 電子與信息學(xué)報(bào), 2006, 28(11): 2186-2190.
引用本文: 王倫耀, 夏銀水, 葉錫恩. 高性能半靜態(tài)雙邊沿D觸發(fā)器[J]. 電子與信息學(xué)報(bào), 2006, 28(11): 2186-2190.
Wang Lun-yao, XiaYin-shui, Ye Xi-en. Design of High Performance Semi-Static Double Edge-Triggered Flip-Flops[J]. Journal of Electronics & Information Technology, 2006, 28(11): 2186-2190.
Citation: Wang Lun-yao, XiaYin-shui, Ye Xi-en. Design of High Performance Semi-Static Double Edge-Triggered Flip-Flops[J]. Journal of Electronics & Information Technology, 2006, 28(11): 2186-2190.

高性能半靜態(tài)雙邊沿D觸發(fā)器

Design of High Performance Semi-Static Double Edge-Triggered Flip-Flops

  • 摘要: 在分析現(xiàn)有靜態(tài)結(jié)構(gòu)雙邊沿觸發(fā)器和動(dòng)態(tài)結(jié)構(gòu)雙邊沿觸發(fā)器優(yōu)缺點(diǎn)的基礎(chǔ)上,該文提出了半靜態(tài)結(jié)構(gòu)雙邊沿觸發(fā)器設(shè)計(jì)。PSPICE模擬表明,新設(shè)計(jì)功能正確。與以往一些設(shè)計(jì)相比,新設(shè)計(jì)在功耗、速度、功耗延遲積以及減少M(fèi)OS晶體管使用數(shù)目等方面都具有明顯的優(yōu)勢,從而使新設(shè)計(jì)具有良好的綜合性能。該文的另一個(gè)貢獻(xiàn)是對(duì)雙邊沿觸發(fā)器性能的測試方法進(jìn)行了探討,提出了測試雙邊沿觸發(fā)器最高頻率的新方法。
  • Pedram M. Power minimization in IC Design: Principles and applications[J].ACM Trans. on Design Automation.1996, 1(1):3-56[2]Sakurai T.[J].Kuroda T. Low-power circuits design for multimedia CMOS VLSIs. In Proc. Synthesis and System Integration of Mixed Technologies, Fukuoka, Japan.1996,:-Llopis R P, Sachdev M. Low power, testable dual edge triggered flip-flops. Int. Symp. Low Power Electronics and Design, Monterey CA USA, 1996: 341-345.[3]Chung W, Lo T, Sachdev M. A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops[J].IEEE Trans. on Very Scale Integration(VLSI) Systems.2002, 10(6):913-918[4]Pedram M, Wu Q, Wu X. A new design of double edge triggered flip-flops. in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 1998: 417-421.[5]Blair G M. Low-power double-triggered flip-flops. ElectronicLetters, 1997, 33(10): 845-847.[6]Strollo A G, Napoli E, Cimino C. Low power double edge-triggered flip-flop using one latch[J].Electronic Letters.1999, 35(3):187-188[7]Hossain R, Wornski L D, Albicki A. Low power design using double edge triggered Flip-flopd. IEEE Trans. on Very Scale Integration(VLSI) Systems, 1994, 10(6): 261-265.[8]王倫耀, 吳訓(xùn)威, 葉錫恩. 新型半靜態(tài)低功耗D觸發(fā)器設(shè)計(jì). 電路與系統(tǒng)學(xué)報(bào), 2004, 9(6): 26-28.[9]Manolescu M, I-Pei Lin. Low-power half-static flip-flop structure. In Proc. Int. Semicond. Conf., Sinaia, Romania, 2000: 211-214.[10]Qiu X H.[J].Chen H Y. Discussion on the low-power latches and flip-flops. Int. Conf. on Solid-State Integrated Circuit Technology, Beijing, China.1998,:-[11]Mishra S M, Rofail S S, Yeo K S. Design of high performance double edge-triggered flip-flops[J].IEE Proc. Circuits Devices Systems.2000, 147(5):283-290[12]Kim S, Kim J, Hwang S Y. New path balancing algorithm for glitch power reduction[J].IEE Proc. Circuits Devices Systems.2001, 148(3):151-156
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出版歷程
  • 收稿日期:  2005-03-11
  • 修回日期:  2005-08-30
  • 刊出日期:  2006-11-19

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