新型CMOS JK觸發(fā)器
Novel CMOS JK Flip-Flop
-
摘要: 該文以雙反相器閂鎖電路為基本存貯單元,采用開關級設計方法設計出一種新型的CMOS JK觸發(fā)器。與傳統(tǒng)設計相比,新設計具有較簡單的結(jié)構(gòu)、較少的元件以及較快的工作速度。Abstract: Taking the latch composed of two inverters as basic storage unit, this paper proposes a novel CMOS JK flip-flop based on the design at switch level. The new design has simpler configuration with less devices and faster working speed in comparing with the traditional design.
-
Telllez G E, Farrah A, Sarrafzadeh M. Activity-driven clock design for low power circuits. Proc. IEEE ICCD, TX, USA, 1995,11: 62- 65.[2]王倫耀,吳訓威.主從型D觸發(fā)器的動態(tài)功耗分析.浙江大學學報(理學版), 2003,30(1):35-40.[3]Wu X (吳訓威), Wei J (韋健). CMOS edge-triggered flip-flop using one latch[J].Electron. Lett.1998, 34 (16):1581-[4]Wu X (吳訓威). Theory of transmission switches and its application to design of CMOS digital circuits[J].International Journal of Circuit Theory and Application.1992, 20(4):349-[5]Rabaey J M. Digital Integrated Circuits: A Design Perspective.New York: Prentice-Hall Inc. 1996:60 - 62. -
計量
- 文章訪問數(shù): 2549
- HTML全文瀏覽量: 189
- PDF下載量: 969
- 被引次數(shù): 0
下載:
