基于CPLD／FPGA的AES算法混合流水實現(xiàn)
The Hybrid Pipelining Implementation of AES in the Feedback Mode Based on CPLD/FPGA
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摘要: 在加解密算法的硬件實現(xiàn)中,使用流水線結(jié)構(gòu)可以顯著地提高加密解密速度,但是由于這類結(jié)構(gòu)并不適合于大多數(shù)的反饋模式,因而此類結(jié)構(gòu)在當(dāng)前密碼學(xué)中的應(yīng)用較少。為此,該文采用一種補償手段,基于交叉CBC(Interleaved Cipher Block Chaining)模式,以混合流水結(jié)構(gòu)成功地實現(xiàn)了AES(Advanced EncryptionStandard)的算法。該方案允許并行處理4個數(shù)據(jù)塊(稱為一次加密或解密),同時兩次加密或解密之間還可實現(xiàn)部分并行。該方案在EP20k300EBC652-1(Ateral公司產(chǎn)品)上已得到成功驗證。
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關(guān)鍵詞:
- AES; 流水線; 混合流水; 硬件實現(xiàn); 加密; 解密
Abstract: Although using pipelining structure in the hardware implementation can generally provide higher throughput, the application of this structure in current cryptography is limited, because they are not suitable for most common feedback modes. This paper puts forward a design of the hybrid pipelining architecture of AES. By including in the AES standard interleaved modes of operation, the design successfully implements the algorithm, which operates in the CBC mode. In this design, four data blocks can be dealt with in parallel (called one-encryption or one-decryption), and at the same time two encryptions or decryptions can be partially overlapped. The design has been implemented on EP20k300EBC652-l device (Ateral). -
Daemen J, Rijmen V. AES Proposal: Rijndael. Available at http:∥csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf[2]Clodowiec P, Gaj K, Bellows P, Schott B. Experimental testing of the gigabit ipSec-compliant implementations of Rijndael and Triple DES using SLAAC-1V FPGA accelerator board.Information Security 4th International Conference, ISC2001Malaga, Spain, October 2001:78 - 92.[3]Gaj K, Chodowiec P. Fast implementation and fair comparison of the final candidates for Advanced Encryption Standard using Field Programmable Gate Arrays. Available at http:∥ece .gmu.edu[4]Nechvatal J, BarkerE, Bassham L, Burr W, Dworkin M, Foti J,Roback E. Report on the development of the Advanced Encryption Standard (AES). Available at http:∥www.nist.gov/aes/ -
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