多值對稱函數(shù)基于二值全加器的電路實現(xiàn)
THE LOGIC SYNTHESIS OF MULTIVALUED SYMMETRIC FUNCTION BASED ON BINARY FULL-ADDER
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摘要: 本文討論了多值對稱函數(shù)的定義和性質(zhì),指出了多值對稱函數(shù)可以按函數(shù)值j分解,而與j相應(yīng)的子函數(shù)Lj必為對稱函數(shù)。且可表示成蛻化多值基本對稱函數(shù)乘積項之和的形式。在此基礎(chǔ)上提出了多值對稱函數(shù)基于二值全加器的邏輯綜合。
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關(guān)鍵詞:
- 多值邏輯; 對稱函數(shù); 邏輯設(shè)計
Abstract: This paper discusses the definition and properties of multivalued symmetric functions, and points out that a multivalued symmetric function can be decomposed according to the value of the function j. The subfunction L j corresponding to j will certainly be a symmetric function, and it may be expressed as the sum-of-products form of degenerated multivalued fundamental symmetric functions. Based on this consideration, the logic synthesis circuit realization for the multivalued symmetric functions based upon full-adders is proposed. -
Chen X(陳偕雄).The Radio and Electronic Engineer, 1983, 53(2): 67-74.[2]Tapia Ma. Int[J].J. Electronics.1989, 67(5):703-715[3]Butler J T, Schueller K A. Worst case number of terms in symmetric multivalued functions, IEEE proc. 21th ISMVL, Victoria: 1991, 94-101.[4]陳偕雄.科技通報,1990, 6(1):1-5.[5]趙小杰,陳偕雄.杭州大學(xué)學(xué)報,1990, 17(4):401-408. -
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