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同步和異步時(shí)序電路的統(tǒng)一設(shè)計(jì)和分析理論

吳訓(xùn)威,  陳曉莉,  金甌

吳訓(xùn)威, 陳曉莉, 金甌. 同步和異步時(shí)序電路的統(tǒng)一設(shè)計(jì)和分析理論[J]. 電子與信息學(xué)報(bào), 1994, 16(4): 365-372.
引用本文: 吳訓(xùn)威, 陳曉莉, 金甌. 同步和異步時(shí)序電路的統(tǒng)一設(shè)計(jì)和分析理論[J]. 電子與信息學(xué)報(bào), 1994, 16(4): 365-372.
Wu Xunwei, Chen Xiaoli, Jin Ou. THE UNIFIED THEORY FOR DESIGNING AND ANALYSING BOTH SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS[J]. Journal of Electronics & Information Technology, 1994, 16(4): 365-372.
Citation: Wu Xunwei, Chen Xiaoli, Jin Ou. THE UNIFIED THEORY FOR DESIGNING AND ANALYSING BOTH SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS[J]. Journal of Electronics & Information Technology, 1994, 16(4): 365-372.

同步和異步時(shí)序電路的統(tǒng)一設(shè)計(jì)和分析理論

THE UNIFIED THEORY FOR DESIGNING AND ANALYSING BOTH SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

  • 摘要: 本文討論了時(shí)鐘信號(hào)的普遍描述和含時(shí)鐘信號(hào)的觸發(fā)器次態(tài)方程,并在此基礎(chǔ)上提出了同步和異步時(shí)序電路的統(tǒng)一設(shè)計(jì)和分析理論。該理論的有效性已由實(shí)例予以證明。
    Abstract: The paper discusses general expresses of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, the unified theory for designing and analysing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.
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  • Rhyne V T. Fundamentals of Digital System Design. Englewood Cliffs, New Jersey: Prentice-Hall, Inc., 1973, 267-272.[2]吳訓(xùn)威,李亦寧.杭州大學(xué)學(xué)報(bào),1983,10(2): 187-189.[3]萬(wàn)棟義.脈沖與數(shù)字電路.北京:高等教育出版社,1986,361-371.[4]陳偕雄,吳訓(xùn)威.杭州大學(xué)學(xué)報(bào),1987,14(3): 301-312.[5]方振賢.電子學(xué)報(bào),1990,18(5): 91-96.[6]吳訓(xùn)威,陳偕雄.Comparison Logic and Its Application in Digital Circuits. Proc. Int. Conf. on[7]CAS. Beijing: 1985, 440-443.
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出版歷程
  • 收稿日期:  1993-03-01
  • 修回日期:  1993-07-13
  • 刊出日期:  1994-07-19

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