嵌入式協(xié)處理器初等函數的快速統(tǒng)一實現
The Unified Fast Implementation of Elementary Functions in the Embeded Coprocessor
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摘要: 該文通過迭代次序的改進和有理近似的引入,提出了改進的CORDIC鐘法。根據改進的CORDIC算法,實現了初等函數的快速統(tǒng)一運算,采用VerilogHDL完成了16位數值協(xié)處理器IP核的設計。該IP核具有規(guī)模較小、高速和控制簡單的特點,非常適合嵌入式應用。Abstract: In this paper, the unified CORDIC algorithm is put forward by the improvement of iterative sequence and the presence of rational approximation. The unified algorithm of elementary functions is implemented with high speed. A coprocessor core using the improved algorithm is built by Verilog HDL. The core is very suitable for embedded application due to its small scale, high speed and simple control.
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