一種高效流水低存儲的JPEG2000編碼芯片設(shè)計
An Efficient Pipeline Design of JPEG2000 Encoder with Low Memory
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摘要: 該文提出了一種高效流水低存儲的JPEG2000編碼芯片的設(shè)計方案。該方案通過采用雙緩存的小波系數(shù)存儲結(jié)構(gòu)，預(yù)速率控制方法，Tier2中的RD斜率值的字節(jié)表示，以減少片上存儲器；對離散小波變換，算術(shù)編碼和位平面編碼使用高度并行流水等設(shè)計結(jié)構(gòu)以提高編碼單元電路速度；字節(jié)地址空間的RD斜率值搜索提高了Tier2的打包速度；對系統(tǒng)實現(xiàn)中的時鐘分配，色度轉(zhuǎn)換，幀存儲器控制進行了優(yōu)化設(shè)計?；谠撛O(shè)計方案的整個編碼芯片已通過FPGA驗證，主要性能參數(shù)：小波類型為5/3，支持最大Tile為256256，最大圖像40964096，碼塊為3232，系統(tǒng)采樣率在Tier1工作時鐘為100MHz時可達45Msamples/s，壓縮圖像與JASPER在壓縮20倍時相比均小于0.5dB，在SMIC.25庫綜合下，等效門為10.9萬，片上RAM為862kb。Abstract: An efficient JPEG2000 encoder is proposed and implemented with high pipeline and low memory architecture. Dual buffers to save the wavelet coefficients, pre-rate allocation and byte expression for Rate-Distortion (RD) slope are used to reduce on-chip memory size. Pipeline and parallel architecture is used in Discrete Wavelet Transform (DWT), Bit-Plane Encoder (BPE) and Arithmetic Encoder (AE) to increase the part circuits encoding speed, searching the truncated RD slope in byte address space increases the packet formatting speed of Tier2. Problems met in system implementation such as clock distribution, SDRAM control of frame buffer and chrominance-transformation are also designed with optimization. The encoder is verified on FPGA platform. Performance of the encoder is as follows: the size of tile is up to 256256 with code block in size of 3232, input sampling rate is up to 45Msamples/s when Tier1 is working at the clock of 100 MHz, difference of the PSNR of images compressed by the proposed encoder and JASPER is less than 0.5dB at the rate of 0.4 bit per sample (bps). Equivalent gates synthesized are about 109k and on-chip RAM is 862kb.
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