基于FPGA和2位串行分布式算法的實時高速二維DCT/IDCT處理器研制
A REAL-TIME 2-D DCT/IDCT PROCESSOR USING FPGAs
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摘要: 本文在W.Li(1991)循環(huán)斜卷積算法和分布式算法的基礎(chǔ)上,通過軟件模擬和具體硬件設(shè)計,利用FPGA完成了可用于高清晰度電視核心解碼器及其它信號與信息處理系統(tǒng)的88二維DCT/IDCT處理器的全部電路設(shè)計工作。它采用一根信號線控制計算DCT/IDCT,其輸入、輸出為12位,內(nèi)部數(shù)據(jù)線及內(nèi)部參數(shù)均為16位。
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關(guān)鍵詞:
- 現(xiàn)場可編程門陣列; 二維DCT/IDCT處理器; 分布式算法
Abstract: Based on the skew-circular convolution distributed algorithm presented by W.Li(1991). A 88 2-D DCT/IDCT processor has been designed using FPGAs, which can be used for HDTV s decoder or other signal and information processing systems. It can be used to calculate either DCT or IDCT depending on a single control line. AM of the input/output are 12-bit and the internal data bus and internal parameters are 16-bit. -
盧煊.等.基于FPGA的實時高速二維DCT/IDCT處理器.徽電子學(xué).1996,(1): 15-19.[2] Li W. A New Algorithm to Compute the DCT and its Inverse. IEEE Trans.on SP, 1991, SP-39(6): 1305-1313.[2]Xilinx Inc. The Programmable Logic Data Book. 1993.[3]孟憲元可編程專用集成電路原理、設(shè)計和應(yīng)用電子工業(yè)出版社, 1995. -
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