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受主型界面態(tài)在深亞微米槽柵PMOSFET中引起退化的研究

任紅霞,  郝躍

任紅霞, 郝躍. 受主型界面態(tài)在深亞微米槽柵PMOSFET中引起退化的研究[J]. 電子與信息學(xué)報(bào), 2002, 24(1): 108-114.
引用本文: 任紅霞, 郝躍. 受主型界面態(tài)在深亞微米槽柵PMOSFET中引起退化的研究[J]. 電子與信息學(xué)報(bào), 2002, 24(1): 108-114.
Ren Hongxia, Hao Yue. Study on the degradation induced by acceptor interface state for deep-sub-micron grooved-bate PMOSFET\s[J]. Journal of Electronics & Information Technology, 2002, 24(1): 108-114.
Citation: Ren Hongxia, Hao Yue. Study on the degradation induced by acceptor interface state for deep-sub-micron grooved-bate PMOSFET\s[J]. Journal of Electronics & Information Technology, 2002, 24(1): 108-114.

受主型界面態(tài)在深亞微米槽柵PMOSFET中引起退化的研究

Study on the degradation induced by acceptor interface state for deep-sub-micron grooved-bate PMOSFET\s

  • 摘要: 界面態(tài)引起的器件特性的退化是深亞微米器件失效的一個(gè)重要因素。本文基于流體動(dòng)力學(xué)能量輸運(yùn)模型,對(duì)溝道雜質(zhì)濃度不同的槽柵和平面PMOSFET中受主型界面態(tài)引起的器件特性的退比進(jìn)行了分析。研究結(jié)果表明同樣濃度的界面態(tài)密度在槽柵器件中引起的器件特性的漂移遠(yuǎn)大于平面器件,且P型受主型界面態(tài)密度對(duì)器件特性的影響也遠(yuǎn)大于N型界面態(tài)。溝道雜質(zhì)濃度不同,界面態(tài)引起的器件特性的退化不同。
    Abstract: The degradation induced by interface state is one main reason for failure occurs in deep-sub-micron MOS devices. Based on the hydrodynamics energy transport model, the degradation induced by acceptor interface state is analyzed for deep-sub-micron grooved-gate and conventional planar PMOSFET with different channel doping density. The simulation results show that the degradation induced by the same interface state density in grooved-gate PMOSFET is larger than that in planar PMOSFET and in both structure devices, the impact of P type acceptor interface state on device performance is far larger than that of N type. It also manifests that the degradation is different for the device with different channel doping density.
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  • C. Hu, Simulating hot-carrier effects on circuit performance, Semiconductor Science Technology,1992, 7(3), B555-B558.[2]J.E. Chung, M. Jeng, J. E. Moon, P. K. Ku, C. Hu, Low-voltage hot-electron currents and degradation in deep-sub-micrometer MOSFETs, IEEE Trans. on Electron Devices, 1990, 37(7),1651-1657.[3]C. Fiegna, H. Iwai, T. Wada, et al., Scaling the MOS transistor below 0.1 m: Methodology,device structures, and technology requirements, IEEE Trans. on Electron Devices, 1994, 41(6),941-949.[4]C. Hu, S. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, K. W. Terrill, Hot-electron-induced MOSFET degradation-model, monitor and improvement, IEEE Trans. on Electron Devices, 1985, 32(2),375-385.[5]H.I. Kimura, J. Tanaka, H. Noda, Short-channel-effect-suppressed sub-0.1-m grooved-gate MOSFETs with W gate, IEEE Trans. on Electron Devices, 1995, 42(1), 94-99.[6]Paul-Henri Bricout, Emmanuel Dubois, Short-channel effect immunity and current capability of sub-0.1-micron MOSFETs using a recessed channel, IEEE Trans. on Electron Devices, 1996,43(8), 1251-1255.[7]R. Woltjer, G. M. Paulzen, H. G. Pomp, H. Lifka, P. H. Woerlee, Three hot-carrier degradation mechanisms in deep-submicron PMOSFETs, IEEE Trans. on Electron Devices, 1995, 42(1),109-114.[8]Technology Modeling Associates, Inc. Medici Two-Dimensional Device Simulation Program Version 2.3 Users Manual, Vol.1, Feb 1997Technology Modeling Associates, Inc. TSUPREM-4 Two-Dimensional Process Simulation Program Version 6.5 User Manual , May 1997[9]S. Tam, P. Ko, C. Hu, Luck-electron model of channel hot-electron injection in MOSFETs, IEEE Trans. on Electron Devices, 31(9), 1984, 1116-1125.[10]任紅霞,郝躍,許冬崗,槽柵NMOSFET抗熱載流子效應(yīng)的研究,物理學(xué)報(bào),2000,49(7),741-748.
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出版歷程
  • 收稿日期:  2000-02-23
  • 修回日期:  2000-07-06
  • 刊出日期:  2002-01-19

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